优化截断嵌入式编码(Embedded block coding with optimized truncation,EBCOT)是JPEG2000的核心,EBCOT所采用的基于码块的率失真优化方式为实现图像感兴趣区(Region of interest,ROI)编码提供了良好的基础.本文分析了其中具有代表性的...优化截断嵌入式编码(Embedded block coding with optimized truncation,EBCOT)是JPEG2000的核心,EBCOT所采用的基于码块的率失真优化方式为实现图像感兴趣区(Region of interest,ROI)编码提供了良好的基础.本文分析了其中具有代表性的隐式ROI编码算法,并提出了一种改进方法.通过构造加权函数,合理地为ROI码块分配权重,在保证ROI信息被优先编码的同时,降低ROI码块中背景区域小波系数的影响,提高了重建图像ROI的质量.实验结果表明,算法在低码率下重建图像ROI质量提高明显,在高码率下也能够很好兼顾重建图像背景区域的质量.展开更多
The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of e...The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.展开更多
文摘优化截断嵌入式编码(Embedded block coding with optimized truncation,EBCOT)是JPEG2000的核心,EBCOT所采用的基于码块的率失真优化方式为实现图像感兴趣区(Region of interest,ROI)编码提供了良好的基础.本文分析了其中具有代表性的隐式ROI编码算法,并提出了一种改进方法.通过构造加权函数,合理地为ROI码块分配权重,在保证ROI信息被优先编码的同时,降低ROI码块中背景区域小波系数的影响,提高了重建图像ROI的质量.实验结果表明,算法在低码率下重建图像ROI质量提高明显,在高码率下也能够很好兼顾重建图像背景区域的质量.
基金Supported in part by the "863" Program (No.2003 AA1ZB10)
文摘The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.
