The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and a...The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.展开更多
Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the deriv...Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.展开更多
This paper analyses the synchronization problem of a generator onto power system without satisfying synchronization condition. The main focus of the paper is on the impact of the dc component of the current in the hig...This paper analyses the synchronization problem of a generator onto power system without satisfying synchronization condition. The main focus of the paper is on the impact of the dc component of the current in the high voltage circuit breaker during its close-open operating cycle. Using real time measurements of currents/voltages and angles during the close-opening cycle of high voltage generator circuit breaker and the impact of the dc component of current in context of interrupting large magnitude of current from the circuit breaker. In addition, the paper describes a study case model and the results of simulations performed using the software EMTP-ATP of an actual incident that occurred during the inadvertent synchronization of a large 339 MW, 24 kV generator to the grid.展开更多
The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timi...The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.展开更多
This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the ...This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.展开更多
According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ter...According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.展开更多
Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple val...Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple valued logic circuits.展开更多
As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemente...As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.展开更多
In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based techni...In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.展开更多
A general method of calculating the saturable leakage reactances of squirrelcage asynchronous motors is presented.The method synthesized the variety of effectswhich affect the saturation of leakage magnetic circuit.An...A general method of calculating the saturable leakage reactances of squirrelcage asynchronous motors is presented.The method synthesized the variety of effectswhich affect the saturation of leakage magnetic circuit.And the saturable reactances canbe precisely evaluated in any running condition.The computation results of Y-series mo-tors are in good agreement with the test ones.展开更多
对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述。本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用T em pura的程序B表示对该电路的特性描述。公式P B引入来证明...对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述。本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用T em pura的程序B表示对该电路的特性描述。公式P B引入来证明电路的正确性,这里P是电路的初始状态,是从Ws中抽取的,另外还要从Ws提取输出等式。这样,一旦证明了P B,就能证明实现满足规格描述。最后,给出了一个例子来说明此证明方法。展开更多
A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous compa...A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous comparator unit,and asynchronous selector unit are proposed.A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process.At a supply voltage of 5V,when it operates at 20MHz,the power consumption is 75.5mW.The processor has no dynamic power consumption when it awaits an opportunity in sleep mode.The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19.18ns is only 82% of the worst-case response time 23.37ns.Compared with the synchronous 4-bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.展开更多
The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents...The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.展开更多
中压设备是列车上较大功率的设备,这些设备分散在列车各系统中,由辅助供电系统集中为其供电。由于电感效应,中压设备启动时的峰值电流会对辅助供电系统的安全性和稳定性产生不利影响。为保证列车辅助供电系统稳定、可靠运行,需要有效地...中压设备是列车上较大功率的设备,这些设备分散在列车各系统中,由辅助供电系统集中为其供电。由于电感效应,中压设备启动时的峰值电流会对辅助供电系统的安全性和稳定性产生不利影响。为保证列车辅助供电系统稳定、可靠运行,需要有效地控制中压设备启动时的峰值电流。基于列车控制与管理系统(TCMS,Train Control and Management System)的控制逻辑,研究列车上电自检阶段中压设备错时顺序启动控制方法,列车运行中空调压缩机错时启动控制方法,以及辅助供电系统故障工况下中压设备减载启动控制方法,避免中压负载峰值电流叠加对辅助供电系统造成的不良影响,确保在故障情况下有足够的辅助供电能力。通过实验室仿真测试和运营线上实车试验,初步验证了在辅助供电备用率和启动峰值电流的限制约束下,列车中压设备启动控制方法的有效性。展开更多
Two types of handshaking circuits are proposed to implement the asynchronous communication between two processing elements in the wavefront array processors. After correcting the flaws in the original design, these ci...Two types of handshaking circuits are proposed to implement the asynchronous communication between two processing elements in the wavefront array processors. After correcting the flaws in the original design, these circuits make the system more robust and flexible. These circuits have compact architectures and are of higher performance. Besides, compared with other handshaking circuits, these designs are more suitable for FPGA.展开更多
基金Supported by National Natural Science Foundation of Zhejiang Province
文摘The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.
基金Supported by the NSF of China (# 69773034) and DARPA under contract # F33615-95-C-1627
文摘Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.
文摘This paper analyses the synchronization problem of a generator onto power system without satisfying synchronization condition. The main focus of the paper is on the impact of the dc component of the current in the high voltage circuit breaker during its close-open operating cycle. Using real time measurements of currents/voltages and angles during the close-opening cycle of high voltage generator circuit breaker and the impact of the dc component of current in context of interrupting large magnitude of current from the circuit breaker. In addition, the paper describes a study case model and the results of simulations performed using the software EMTP-ATP of an actual incident that occurred during the inadvertent synchronization of a large 339 MW, 24 kV generator to the grid.
文摘The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.
文摘This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.
基金Supported by the National Natural Science Foundation of Zhejiang Province,China.
文摘According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.
文摘Propose the sequential circuits with the ternary D-ffs in series^1. Discuss the equivalence between the sequential circuits with the p-valued flip-flops in series and in parallel as a part of studying the multiple valued logic circuits.
文摘As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.
基金Supported by NSF of the United States under contract 5978 East Asia and Pacific Program 9602485
文摘In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.
文摘A general method of calculating the saturable leakage reactances of squirrelcage asynchronous motors is presented.The method synthesized the variety of effectswhich affect the saturation of leakage magnetic circuit.And the saturable reactances canbe precisely evaluated in any running condition.The computation results of Y-series mo-tors are in good agreement with the test ones.
文摘对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述。本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用T em pura的程序B表示对该电路的特性描述。公式P B引入来证明电路的正确性,这里P是电路的初始状态,是从Ws中抽取的,另外还要从Ws提取输出等式。这样,一旦证明了P B,就能证明实现满足规格描述。最后,给出了一个例子来说明此证明方法。
文摘A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous comparator unit,and asynchronous selector unit are proposed.A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process.At a supply voltage of 5V,when it operates at 20MHz,the power consumption is 75.5mW.The processor has no dynamic power consumption when it awaits an opportunity in sleep mode.The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19.18ns is only 82% of the worst-case response time 23.37ns.Compared with the synchronous 4-bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.
基金the Strategic Priority Research Program of Chinese Academy of Sciences(No.XDA18000000)the National Natural Science Foundation of China(No.61732018,61872335).
文摘The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.
文摘中压设备是列车上较大功率的设备,这些设备分散在列车各系统中,由辅助供电系统集中为其供电。由于电感效应,中压设备启动时的峰值电流会对辅助供电系统的安全性和稳定性产生不利影响。为保证列车辅助供电系统稳定、可靠运行,需要有效地控制中压设备启动时的峰值电流。基于列车控制与管理系统(TCMS,Train Control and Management System)的控制逻辑,研究列车上电自检阶段中压设备错时顺序启动控制方法,列车运行中空调压缩机错时启动控制方法,以及辅助供电系统故障工况下中压设备减载启动控制方法,避免中压负载峰值电流叠加对辅助供电系统造成的不良影响,确保在故障情况下有足够的辅助供电能力。通过实验室仿真测试和运营线上实车试验,初步验证了在辅助供电备用率和启动峰值电流的限制约束下,列车中压设备启动控制方法的有效性。
文摘Two types of handshaking circuits are proposed to implement the asynchronous communication between two processing elements in the wavefront array processors. After correcting the flaws in the original design, these circuits make the system more robust and flexible. These circuits have compact architectures and are of higher performance. Besides, compared with other handshaking circuits, these designs are more suitable for FPGA.
