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Performance Characterization of Parallel Game-tree Search Application Crafty
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作者 谭膺 罗克露 +1 位作者 陈玉荣 张益民 《Journal of Electronic Science and Technology of China》 2006年第2期155-160,共6页
Game-tree search plays an important role in the field of Artificial Intelligence (AI). In this paper, we characterize one parallel game-tree search workload in chess: the latest version of Crafty, a state of art pr... Game-tree search plays an important role in the field of Artificial Intelligence (AI). In this paper, we characterize one parallel game-tree search workload in chess: the latest version of Crafty, a state of art program, on two Intel Xeon shared-memory multiprocessor systems. Our analysis shows that Crafty is latency-sensitive and the hash-table and dynamic tree splitting used in Crafty cause large scalability penalties. They consume 35%-50% of the running time on the 4-way system. Furthermore, Crafty is not bandwidth-limited. 展开更多
关键词 performance characterization workload analysis parallel game-tree search computer chess crafty
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A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth
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作者 姚骏 Shinobu Miwa +1 位作者 Hajime Shimada Shinji Tomita 《Journal of Computer Science & Technology》 SCIE EI CSCD 2011年第2期292-301,共10页
Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a c... Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product (EDP) reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures. 展开更多
关键词 dynamic optimization energy saving FINE-GRAINED pipeline stage unification workload analysis
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