In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal respon...In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal response. We present a new multiobjective genetic algorithm（MOGA） which uses a single objective sorting（SOS） method for constructing the non-dominated set to solve this multi-objective interconnect optimization problem. The MOGA/SOS optimal algorithm provides a smooth trade-off among signal delay, wave form, and routing area. Furthermore, we use a new method to calculate the lower bound of crosstalk. Extensive experimental results show that our algorithm is scalable with problem size. Furthermore, compared to the solution based on an Elmore delay model, our solution reduces the total routing area by up to 30%, the delay to the critical sinks by up to 25%, while further improving crosstalk up to 25.73% on average.展开更多
A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (...A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances include the timing delay and the quality of signal waveform. The experimental results show that our proposed approach is scalable and obtains better performance than SP-tree and graph-RTBW approaches for the test signal nets.展开更多
基金Supported by the National Natural Science Foundation of China (90307017)
文摘In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal response. We present a new multiobjective genetic algorithm（MOGA） which uses a single objective sorting（SOS） method for constructing the non-dominated set to solve this multi-objective interconnect optimization problem. The MOGA/SOS optimal algorithm provides a smooth trade-off among signal delay, wave form, and routing area. Furthermore, we use a new method to calculate the lower bound of crosstalk. Extensive experimental results show that our algorithm is scalable with problem size. Furthermore, compared to the solution based on an Elmore delay model, our solution reduces the total routing area by up to 30%, the delay to the critical sinks by up to 25%, while further improving crosstalk up to 25.73% on average.
基金The National Natural Science Foundation of China (No. 90307017)
文摘A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances include the timing delay and the quality of signal waveform. The experimental results show that our proposed approach is scalable and obtains better performance than SP-tree and graph-RTBW approaches for the test signal nets.
