In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-sta...In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.展开更多
The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network con...The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.展开更多
电压控制型逆变器VCI(voltage-controlled inverters)在弱电网下表现出更强的稳定性,有望在可再生能源发电中得到更广泛的应用。然而,VCI的有功功率控制带宽通常低于电流控制并网逆变器CCI(current-controlled inverter)。随着电网阻抗...电压控制型逆变器VCI(voltage-controlled inverters)在弱电网下表现出更强的稳定性,有望在可再生能源发电中得到更广泛的应用。然而,VCI的有功功率控制带宽通常低于电流控制并网逆变器CCI(current-controlled inverter)。随着电网阻抗增大和电网强度进一步降低,其调节时间甚至将长达数秒,难以满足可再生能源发电最大功率点跟踪MPPT(maximum power point tracking)的要求。此外,现有的以功率环改造为特点的VCI有功功率快速控制方法,则可能导致弱电网下VCI稳定性损失。针对这一问题,建立了VCI并网系统的详细输入-输出模型,揭示了弱电网下VCI功率环改造法面临稳定性和快速性矛盾的根源,并提出了一种基于外环改造和功率指令前置滤波的VCI有功功率快速控制方法,能够有效提升VCI有功功率控制带宽,且不影响其弱电网下的稳定性,进一步实现了基于VCI的MPPT控制;针对短路容量比和电网阻抗大幅波动对所提控制的影响,又提出了一种基于电网阻抗在线辨识的VCI有功功率快速控制自适应方法。最后,实验结果验证了所提方法的有效性。展开更多
基金The National High Technology Research and Development Program of China (863 Program)(No. 2007AA01Z2a5)the National Natural Science Foundation of China (No. 60806027,61076073)Specialized Research Fund for the Doctoral Program of Higher Education (No.20090092120012)
文摘In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.
基金supported by Iran Telecommunication Research Center under Grant No. 4222/500
文摘The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.
文摘电压控制型逆变器VCI(voltage-controlled inverters)在弱电网下表现出更强的稳定性,有望在可再生能源发电中得到更广泛的应用。然而,VCI的有功功率控制带宽通常低于电流控制并网逆变器CCI(current-controlled inverter)。随着电网阻抗增大和电网强度进一步降低,其调节时间甚至将长达数秒,难以满足可再生能源发电最大功率点跟踪MPPT(maximum power point tracking)的要求。此外,现有的以功率环改造为特点的VCI有功功率快速控制方法,则可能导致弱电网下VCI稳定性损失。针对这一问题,建立了VCI并网系统的详细输入-输出模型,揭示了弱电网下VCI功率环改造法面临稳定性和快速性矛盾的根源,并提出了一种基于外环改造和功率指令前置滤波的VCI有功功率快速控制方法,能够有效提升VCI有功功率控制带宽,且不影响其弱电网下的稳定性,进一步实现了基于VCI的MPPT控制;针对短路容量比和电网阻抗大幅波动对所提控制的影响,又提出了一种基于电网阻抗在线辨识的VCI有功功率快速控制自适应方法。最后,实验结果验证了所提方法的有效性。
