In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-sta...In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.展开更多
The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network con...The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.展开更多
基金The National High Technology Research and Development Program of China (863 Program)(No. 2007AA01Z2a5)the National Natural Science Foundation of China (No. 60806027,61076073)Specialized Research Fund for the Doctoral Program of Higher Education (No.20090092120012)
文摘In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.
基金supported by Iran Telecommunication Research Center under Grant No. 4222/500
文摘The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.
