This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated us...This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.展开更多
We investigate the effects of （N,N’-diphenyl）-N,N’-bis（1-naphthyl）-1,1’-biphenyl-4,4’-diamine （NPB） buffer layers on charge collection in inverted ZnO/MEH-PPV hybrid devices. The insertion of a 3-nm NPB thin...We investigate the effects of （N,N’-diphenyl）-N,N’-bis（1-naphthyl）-1,1’-biphenyl-4,4’-diamine （NPB） buffer layers on charge collection in inverted ZnO/MEH-PPV hybrid devices. The insertion of a 3-nm NPB thin layer enhances the efficiency of charge collection by improving charge transport and reducing the interface energy barrier, resulting in better device performances. S-shaped light J–V curve appears when the thickness of the NPB layer reaches 25 nm, which is induced by the inefficient charge extraction from MEH-PPV to Ag. Capacitance–voltage measurements are performed to further investigate the influence of the NPB layer on charge collection from both simulations and experiments.展开更多
A new Single-Resistance-Controlled (SRC) sinusoidal oscillator using single Voltage Differencing-Differential Input Buffered Amplifier (VD-DIBA), only four passive components (two capacitors and two resistors), is pre...A new Single-Resistance-Controlled (SRC) sinusoidal oscillator using single Voltage Differencing-Differential Input Buffered Amplifier (VD-DIBA), only four passive components (two capacitors and two resistors), is presented. The proposed structure provides the following advantageous features: 1) independent control of oscillation frequency and condition of oscillation and 2) low active and passive sensitivities. The effects of non-idealities of the VD-DIBA on the proposed oscillator have also been investigated. The proposed SRC sinusoidal oscillator has been checked for robustness using Monte-Carlo simulation. SPICE simulation results have been included using 0.35 μm MIETEC technology to confirm the validity of the proposed SRC sinusoidal oscillator.展开更多
文摘This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.
基金Project supported by the National Basic Research Program of China(Grant No.2010CB327704)the National Natural Science Foundation of China(Grant No.51272022)+2 种基金the Program for New Century Excellent Talents in University of Ministry of Education of China(Grant No.NCET-10-0220)the Research Fund for the Doctoral Program of Higher Education,China(Grant No.20120009130005)the Fundamental Research Funds for the Central Universities,China(Grant No.2012JBZ001)
文摘We investigate the effects of （N,N’-diphenyl）-N,N’-bis（1-naphthyl）-1,1’-biphenyl-4,4’-diamine （NPB） buffer layers on charge collection in inverted ZnO/MEH-PPV hybrid devices. The insertion of a 3-nm NPB thin layer enhances the efficiency of charge collection by improving charge transport and reducing the interface energy barrier, resulting in better device performances. S-shaped light J–V curve appears when the thickness of the NPB layer reaches 25 nm, which is induced by the inefficient charge extraction from MEH-PPV to Ag. Capacitance–voltage measurements are performed to further investigate the influence of the NPB layer on charge collection from both simulations and experiments.
文摘A new Single-Resistance-Controlled (SRC) sinusoidal oscillator using single Voltage Differencing-Differential Input Buffered Amplifier (VD-DIBA), only four passive components (two capacitors and two resistors), is presented. The proposed structure provides the following advantageous features: 1) independent control of oscillation frequency and condition of oscillation and 2) low active and passive sensitivities. The effects of non-idealities of the VD-DIBA on the proposed oscillator have also been investigated. The proposed SRC sinusoidal oscillator has been checked for robustness using Monte-Carlo simulation. SPICE simulation results have been included using 0.35 μm MIETEC technology to confirm the validity of the proposed SRC sinusoidal oscillator.
