Traffic forecasting with high precision aids Intelligent Transport Systems(ITS)in formulating and optimizing traffic management strategies.The algorithms used for tuning the hyperparameters of the deep learning models...Traffic forecasting with high precision aids Intelligent Transport Systems(ITS)in formulating and optimizing traffic management strategies.The algorithms used for tuning the hyperparameters of the deep learning models often have accurate results at the expense of high computational complexity.To address this problem,this paper uses the Tree-structured Parzen Estimator(TPE)to tune the hyperparameters of the Long Short-term Memory(LSTM)deep learning framework.The Tree-structured Parzen Estimator(TPE)uses a probabilistic approach with an adaptive searching mechanism by classifying the objective function values into good and bad samples.This ensures fast convergence in tuning the hyperparameter values in the deep learning model for performing prediction while still maintaining a certain degree of accuracy.It also overcomes the problem of converging to local optima and avoids timeconsuming random search and,therefore,avoids high computational complexity in prediction accuracy.The proposed scheme first performs data smoothing and normalization on the input data,which is then fed to the input of the TPE for tuning the hyperparameters.The traffic data is then input to the LSTM model with tuned parameters to perform the traffic prediction.The three optimizers:Adaptive Moment Estimation(Adam),Root Mean Square Propagation(RMSProp),and Stochastic Gradient Descend with Momentum(SGDM)are also evaluated for accuracy prediction and the best optimizer is then chosen for final traffic prediction in TPE-LSTM model.Simulation results verify the effectiveness of the proposed model in terms of accuracy of prediction over the benchmark schemes.展开更多
Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
针对三值光学计算机(ternary optical computer,TOC)中可变位数改良符号数字(modified signed digit,MSD)加法器所面临的移位效率问题,提出了一种全新的数据移位方式,并设计了相应的可变距离移位寄存器.该移位方式为寄存器每个位的输入...针对三值光学计算机(ternary optical computer,TOC)中可变位数改良符号数字(modified signed digit,MSD)加法器所面临的移位效率问题,提出了一种全新的数据移位方式,并设计了相应的可变距离移位寄存器.该移位方式为寄存器每个位的输入线和输出线分别设置了对应数据总线不同位线的跨接旁路,每个旁路的电子开关由一位锁存器控制,通过给锁存器赋值来改变移位的距离,从而实现指定距离的快速移位,解决了当前移位寄存器因采用D触发器(D flip-flop,DFF)串连结构只能实现逐位移动而效率低下的问题.讨论了该新型移位技术的原理和可变距离移位寄存器的实现方案,给出了6个可变距离移位寄存器实例,并将这些实例与传统移位寄存器进行了对比实验.研究结果表明,该新型移位技术在时钟频率、移位延迟、硬件资源消耗和功耗方面明显优于传统移位技术,能够显著提升三值光学计算机中MSD加法器的性能.展开更多
The advent of Grover’s algorithm presents a significant threat to classical block cipher security,spurring research into post-quantum secure cipher design.This study engineers quantum circuit implementations for thre...The advent of Grover’s algorithm presents a significant threat to classical block cipher security,spurring research into post-quantum secure cipher design.This study engineers quantum circuit implementations for three versions of the Ballet family block ciphers.The Ballet‑p/k includes a modular-addition operation uncommon in lightweight block ciphers.Quantum ripple-carry adder is implemented for both“32+32”and“64+64”scale to support this operation.Subsequently,qubits,quantum gates count,and quantum circuit depth of three versions of Ballet algorithm are systematically evaluated under quantum computing model,and key recovery attack circuits are constructed based on Grover’s algorithm against each version.The comprehensive analysis shows:Ballet-128/128 fails to NIST Level 1 security,while when the resource accounting is restricted to the Clifford gates and T gates set for the Ballet-128/256 and Ballet-256/256 quantum circuits,the design attains Level 3.展开更多
This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability o...This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.展开更多
In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage...In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.展开更多
Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based tr...Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive hi...Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.展开更多
The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Lar...The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.展开更多
Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed an...Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.展开更多
文摘Traffic forecasting with high precision aids Intelligent Transport Systems(ITS)in formulating and optimizing traffic management strategies.The algorithms used for tuning the hyperparameters of the deep learning models often have accurate results at the expense of high computational complexity.To address this problem,this paper uses the Tree-structured Parzen Estimator(TPE)to tune the hyperparameters of the Long Short-term Memory(LSTM)deep learning framework.The Tree-structured Parzen Estimator(TPE)uses a probabilistic approach with an adaptive searching mechanism by classifying the objective function values into good and bad samples.This ensures fast convergence in tuning the hyperparameter values in the deep learning model for performing prediction while still maintaining a certain degree of accuracy.It also overcomes the problem of converging to local optima and avoids timeconsuming random search and,therefore,avoids high computational complexity in prediction accuracy.The proposed scheme first performs data smoothing and normalization on the input data,which is then fed to the input of the TPE for tuning the hyperparameters.The traffic data is then input to the LSTM model with tuned parameters to perform the traffic prediction.The three optimizers:Adaptive Moment Estimation(Adam),Root Mean Square Propagation(RMSProp),and Stochastic Gradient Descend with Momentum(SGDM)are also evaluated for accuracy prediction and the best optimizer is then chosen for final traffic prediction in TPE-LSTM model.Simulation results verify the effectiveness of the proposed model in terms of accuracy of prediction over the benchmark schemes.
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
基金State Key Lab of Processors,Institute of Computing Technology,Chinese Academy of Sciences(CLQ202516)the Fundamental Research Funds for the Central Universities of China(3282025047,3282024051,3282024009)。
文摘The advent of Grover’s algorithm presents a significant threat to classical block cipher security,spurring research into post-quantum secure cipher design.This study engineers quantum circuit implementations for three versions of the Ballet family block ciphers.The Ballet‑p/k includes a modular-addition operation uncommon in lightweight block ciphers.Quantum ripple-carry adder is implemented for both“32+32”and“64+64”scale to support this operation.Subsequently,qubits,quantum gates count,and quantum circuit depth of three versions of Ballet algorithm are systematically evaluated under quantum computing model,and key recovery attack circuits are constructed based on Grover’s algorithm against each version.The comprehensive analysis shows:Ballet-128/128 fails to NIST Level 1 security,while when the resource accounting is restricted to the Clifford gates and T gates set for the Ballet-128/256 and Ballet-256/256 quantum circuits,the design attains Level 3.
基金supported by the Grant number 600/1792 from the vice presidency of research and technology of Shahid Beheshti University,G.C
文摘This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
基金supported by National Natural Science Foundation of China(No.51307141)partly by the State Key Laboratory of Intense Pulsed Radiation Simulation(Northwest Institute of Nuclear Technology)under Contract SKLIPR 1206
文摘In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.
文摘Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
文摘Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.
文摘The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.
文摘Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
