In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value...In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.展开更多
We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overl...We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.展开更多
The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface...The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.展开更多
An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented...An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.展开更多
In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering...In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.展开更多
In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along wit...In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.展开更多
The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state cu...The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.展开更多
Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control tec...Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.展开更多
The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress...The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFB0400 300)the National Natural Science Foundation of China(Grant Nos.61574110,61574112,and 61474091)
文摘In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities of China(Grant No.20110203110012)
文摘We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376099,11235008,and 61205003)
文摘The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.
文摘An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China (Grant No. 708083)the Fundamental Research Funds for the Central Universities (Grant No. 20110203110012)
文摘In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.
文摘In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.
基金supported by the National Natural Science Foundation of China(Grant Nos.61076113 and 61274085)the Research Grants Council of Hong Kong,China(Grant No.7133/07E)
文摘The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.
文摘Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.
基金Project supported by the National High Technology Research and Development Program of China （Grant No 2003AA1Z1630） and the National Natural Science Foundation of China （Grant No 60376024）.
文摘The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.
