Under different conditions, the highest detection probability should be acquired while receiving laser echo during laser pulse range finding. The threshold voltage of the signal detection can be set corresponding ...Under different conditions, the highest detection probability should be acquired while receiving laser echo during laser pulse range finding. The threshold voltage of the signal detection can be set corresponding to different conditions by using resistor network. As a feedback loop, automatic noise threshold circuit could change the threshold voltage following the noise level. The threshold can track the noise closely, rapidly and accurately by adopting this combination. Therefore, the receiving capability of laser echo receiving system will be maximized, and it can detect weaker laser pulse from noise.展开更多
As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on ...As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.展开更多
Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the c...Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.展开更多
This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the perfo...This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.展开更多
由于传统的互补金属-氧化物-半导体(Complementary Metal Oxide Semiconductor,CMOS)神经元电路与生物学的契合性较差且电路复杂,提出了一种基于忆阻器的多端口输入的泄露-整合-激发(Leaky-Integrate-Fire,LIF)神经元电路。该电路由运...由于传统的互补金属-氧化物-半导体(Complementary Metal Oxide Semiconductor,CMOS)神经元电路与生物学的契合性较差且电路复杂,提出了一种基于忆阻器的多端口输入的泄露-整合-激发(Leaky-Integrate-Fire,LIF)神经元电路。该电路由运放、逻辑门等器件以及忆阻器构成,主要分为信号叠加模块和神经元信号产生模块。通过施加多个双尖峰脉冲信号并调节输入信号的数量和频率,模拟了生物神经元受到的不同程度刺激。研究发现施加到神经元上信号的数量和频率达到一定的值,神经元电路才会输出电压信号,这与生物体中只有受到一定程度的刺激时才会做出反应的现象是一致的。进一步,调节该电路中神经元信号产生模块的阈值电压大小,研究发现输入相同的信号,只有当电路的阈值电压较低时,神经元电路才能输出电压信号,这与生物中不同部位受到相同的刺激,神经元兴奋程度越高,越容易做出反应的现象一致。由此,该文所提出的LIF神经元电路不仅解决了传统电路输入信号单一、输入信号波形与生物信号波形差异大等问题,而且能模拟生物神经元的兴奋程度,这为人工神经网络的设计提供理论依据。展开更多
文摘Under different conditions, the highest detection probability should be acquired while receiving laser echo during laser pulse range finding. The threshold voltage of the signal detection can be set corresponding to different conditions by using resistor network. As a feedback loop, automatic noise threshold circuit could change the threshold voltage following the noise level. The threshold can track the noise closely, rapidly and accurately by adopting this combination. Therefore, the receiving capability of laser echo receiving system will be maximized, and it can detect weaker laser pulse from noise.
基金Sponsored by the Fundamental Research Funds for the Central Universities(Grant No.HIT.NSRIF.2016107)the China Postdoctoral Science Foundation(Grant No.2015M581447)
文摘As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2
文摘Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.
文摘This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.
文摘由于传统的互补金属-氧化物-半导体(Complementary Metal Oxide Semiconductor,CMOS)神经元电路与生物学的契合性较差且电路复杂,提出了一种基于忆阻器的多端口输入的泄露-整合-激发(Leaky-Integrate-Fire,LIF)神经元电路。该电路由运放、逻辑门等器件以及忆阻器构成,主要分为信号叠加模块和神经元信号产生模块。通过施加多个双尖峰脉冲信号并调节输入信号的数量和频率,模拟了生物神经元受到的不同程度刺激。研究发现施加到神经元上信号的数量和频率达到一定的值,神经元电路才会输出电压信号,这与生物体中只有受到一定程度的刺激时才会做出反应的现象是一致的。进一步,调节该电路中神经元信号产生模块的阈值电压大小,研究发现输入相同的信号,只有当电路的阈值电压较低时,神经元电路才能输出电压信号,这与生物中不同部位受到相同的刺激,神经元兴奋程度越高,越容易做出反应的现象一致。由此,该文所提出的LIF神经元电路不仅解决了传统电路输入信号单一、输入信号波形与生物信号波形差异大等问题,而且能模拟生物神经元的兴奋程度,这为人工神经网络的设计提供理论依据。
