A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable...A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
针对现场可编程门阵列(Field Programmable Gate Array,FPGA)电声测试数据采集电路的优化策略进行深入研究。在电声测试领域,数据采集精准性与效率极其关键,而FPGA凭借高性能属性得到广泛应用。在电声测试数据收集阶段,FPGA在采样率和...针对现场可编程门阵列(Field Programmable Gate Array,FPGA)电声测试数据采集电路的优化策略进行深入研究。在电声测试领域,数据采集精准性与效率极其关键,而FPGA凭借高性能属性得到广泛应用。在电声测试数据收集阶段,FPGA在采样率和多通道同步等方面面临难题。为化解这些困扰,制定一系列优化办法,包括高速模数转换器(Analog to Digital Converter,ADC)接口设计事项及多通道并行的架构体系,以增强电路性能,为电声测试给予更可靠且高效的数据收集支撑。展开更多
Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or ...Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.展开更多
基金supported by the Key Techniques of FPGA Architecture under Grant No.9140A08010106QT9201
文摘A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
文摘针对现场可编程门阵列(Field Programmable Gate Array,FPGA)电声测试数据采集电路的优化策略进行深入研究。在电声测试领域,数据采集精准性与效率极其关键,而FPGA凭借高性能属性得到广泛应用。在电声测试数据收集阶段,FPGA在采样率和多通道同步等方面面临难题。为化解这些困扰,制定一系列优化办法,包括高速模数转换器(Analog to Digital Converter,ADC)接口设计事项及多通道并行的架构体系,以增强电路性能,为电声测试给予更可靠且高效的数据收集支撑。
文摘Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.
