A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while r...A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes： mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 μm CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.展开更多
针对SVC(Static Var Compensation,简称SVC)控制系统的同步问题,通过充分利用控制装置硬件资源,设计了一种新型软件锁相环,在DSP(Digital Signal Processing,简称DSP)单元编码实现软件锁相模块,以现场FPGA(Field Programmable Gate Arr...针对SVC(Static Var Compensation,简称SVC)控制系统的同步问题,通过充分利用控制装置硬件资源,设计了一种新型软件锁相环,在DSP(Digital Signal Processing,简称DSP)单元编码实现软件锁相模块,以现场FPGA(Field Programmable Gate Array,简称FPGA),锁相计数器替代复杂的积分环节,产生锁相角θ,配合实现锁相。通过仿真和试验验证,软件锁相环在电压不平衡、电压跌落、频率突变等条件下,仍可快速、可靠的实现锁相,减小触发误差,具有良好的应用效果。展开更多
基金supported by the National Science and Technology Major Project of China(No.2013ZX03006004)the National Natural Science Foundation of China(No.61106025)the CAS/SAFEA International Partnership Program for Creative Research Teams
文摘A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes： mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 μm CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.
文摘针对SVC(Static Var Compensation,简称SVC)控制系统的同步问题,通过充分利用控制装置硬件资源,设计了一种新型软件锁相环,在DSP(Digital Signal Processing,简称DSP)单元编码实现软件锁相模块,以现场FPGA(Field Programmable Gate Array,简称FPGA),锁相计数器替代复杂的积分环节,产生锁相角θ,配合实现锁相。通过仿真和试验验证,软件锁相环在电压不平衡、电压跌落、频率突变等条件下,仍可快速、可靠的实现锁相,减小触发误差,具有良好的应用效果。
