In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution proc...In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.展开更多
Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is...Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is further converted equivalently to an unconstrained binary integer programming problem by a penalty method. A local search method, HSFM, is developed to obtain a discrete local minimizer of the unconstrained binary integer programming problem. Next, an auxiliary function, which has the same global optimal solutions as the unconstrained binary integer programming problem, is constructed, and its properties are studied. We show that applying HSFM to minimize the auxiliary function can escape from previous local optima by the increase of the parameter value successfully. Finally, a discrete dynamic convexized method is developed to solve the hardware/software partitioning problem. Computational results and comparisons indicate that the proposed algorithm can get high-quality solutions.展开更多
Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full...Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.展开更多
This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second met...This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.展开更多
In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed st...In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.展开更多
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design...This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.展开更多
With the rapid development of information technology in the energy industry, the use of information means to integrate and share all kinds of resources, to improve the utilization rate of resources, to achieve the pur...With the rapid development of information technology in the energy industry, the use of information means to integrate and share all kinds of resources, to improve the utilization rate of resources, to achieve the purposes of rational use of resources, cost reduction and efficiency improvement, and to improve the labor efficiency has become the primary task of oilfield information and scientific research management. This paper mainly discusses the application of "enterprise-class professional software and hardware cloud" in scientific research, and mainly discusses the contents of professional software and hardware sharing application, intelligent operation and maintenance, data sharing, remote collaboration, etc., and organically combines information management with scientific research and production management, thus effectively improving the management level of scientific research software and hardware.展开更多
With the progress of the times and the development of information technology, the computer has become a life tool. Due to its intelligent convenience, it is widely used in daily life, but the inevitable failure proble...With the progress of the times and the development of information technology, the computer has become a life tool. Due to its intelligent convenience, it is widely used in daily life, but the inevitable failure problems of the machine, or the loss of the computer and data, and causes immeasurable trouble and loss.展开更多
We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction...We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.展开更多
The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kind...The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.展开更多
The dual-motor controller system is one of the key components in the multi-power architecture of new energy vehicles and is crucial to the safe operation of the vehicle.From the perspective of functional safety,this a...The dual-motor controller system is one of the key components in the multi-power architecture of new energy vehicles and is crucial to the safe operation of the vehicle.From the perspective of functional safety,this article takes the torque safety goal of"avoiding unexpected acceleration of the vehicle due to unexpected acceleration torque"as an example to explore various software and hardware architecture implementation methods,and analysis the test scheme covering multiple stages such as HIL/PowerHIL testing,bench testing and vehicle testing to verify the effectiveness of the safety path.Through the verification of the safety strategy,it provides innovative ideas for the functional safety design and testing of the electric drive control system,which is expected to provide a reference for improving the overall safety of new energy vehicles.展开更多
With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggr...With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.展开更多
This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great me...This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.展开更多
In order to satisfy the ever-increasing energy appetite of the massive battery-powered and batteryless communication devices,radio frequency(RF)signals have been relied upon for transferring wireless power to them.The...In order to satisfy the ever-increasing energy appetite of the massive battery-powered and batteryless communication devices,radio frequency(RF)signals have been relied upon for transferring wireless power to them.The joint coordination of wireless power transfer(WPT)and wireless information transfer(WIT)yields simultaneous wireless information and power transfer(SWIPT)as well as data and energy integrated communication network(DEIN).However,as a promising technique,few efforts are invested in the hardware implementation of DEIN.In order to make DEIN a reality,this paper focuses on hardware implementation of a DEIN.It firstly provides a brief tutorial on SWIPT,while summarising the latest hardware design of WPT transceiver and the existing commercial solutions.Then,a prototype design in DEIN with full protocol stack is elaborated,followed by its performance evaluation.展开更多
This paper introduces an effective software-based FEC redundant packets generating algorithm. The algorithm is based on Reed-Solomon coding over Galois Field. By operating on words of packets and performing polynomial...This paper introduces an effective software-based FEC redundant packets generating algorithm. The algorithm is based on Reed-Solomon coding over Galois Field. By operating on words of packets and performing polynomial multiplication via lookup tables, software coding efficiency is achieved to satisfy the needs of most of computer network applications. The approach to generate lookup tables is detailed.展开更多
Robustness testing for safety-critical embedded software is still a challenge in its nascent stages. In this paper, we propose a practical methodology and implement an environment by employing model-based robustness t...Robustness testing for safety-critical embedded software is still a challenge in its nascent stages. In this paper, we propose a practical methodology and implement an environment by employing model-based robustness testing for embedded software systems. It is a system-level black-box testing approach in which the fault behaviors of embedded software is triggered with the aid of modelbased fault injection by the support of an executable model-driven hardware-in-loop （HIL） testing environment. The prototype implementation of the robustness testing environment based on the proposed approach is experimentally discussed and illustrated by industrial case studies based on several avionics-embedded software systems. The results show that our proposed and implemented robustness testing method and environment are effective to find more bugs, and reduce burdens of testing engineers to enhance efficiency of testing tasks, especially for testing complex embedded systems.展开更多
In this paper, a novel Medium Access Control (MAC) protocol for industrial Wireless Local Area Networks (WLANs) is proposed and studied. The main challenge in industry automation systems is the ultra-low network laten...In this paper, a novel Medium Access Control (MAC) protocol for industrial Wireless Local Area Networks (WLANs) is proposed and studied. The main challenge in industry automation systems is the ultra-low network latency with a target upper bound in the order of 1 ms while maintaining high network reliability and availability. The novelty of the proposed wireless MAC protocol resides in its similar latency performance as its counterpart in wired industrial LAN. First, the functional design of the MAC protocol is introduced. Then its performance results gained from hardware implementation (SystemC and VHDL) on an FPGA platform are presented. Finally, a real-time communication module which achieves the ultra-low latency required in industrial automation is described.展开更多
In this study,a mathematical model of multipath channels is established,and the delay parameters of 10-path models are calculated at 300 m.A multipath-channel hardware simulator based on a field programmable gate arra...In this study,a mathematical model of multipath channels is established,and the delay parameters of 10-path models are calculated at 300 m.A multipath-channel hardware simulator based on a field programmable gate array(FPGA)is designed and verified at 100 k Hz,200 k Hz,500 k Hz,1 MHz,and 24 MHz transmission frequencies.According to the characteristics of the ocean induction coupling chain channel,the orthogonal frequency-division multiplexing(OFDM)algorithm parameters are designed by referring to the wireless communication protocol.The appropriate length cyclic prefix(CP)is added in the OFDM symbol to resist the multipath effect of the seawater channel,and the FPGA hardware transceiver based on the OFDM algorithm is realized.The hardware platform of the ocean induction coupling chain communication system is developed to resist the multipath effect of the seawater channel and tested at 24 MHz.The experimental results show that 800 ns is the best CP length for the developed system,which can effectively resist the multipath effect,with a signal-to-noise ratio above 24 d B and a bit error rate below 1%.This study provides a hardware simulation test platform and an effective method to resist the multipath effect of a seawater channel and improve the transmission performance of the seawater channel.展开更多
Computer numerical control(CNC)system is the base of modern digital and intelligent manufacturing technolo-gy.And opened its architecture and constituted based on PC and Windows operating system(OS)is the main trend o...Computer numerical control(CNC)system is the base of modern digital and intelligent manufacturing technolo-gy.And opened its architecture and constituted based on PC and Windows operating system(OS)is the main trend of CNC sys-tem.However,even if the highest system priority is used in user mode,real-time capability of Windows(2000,NT,XP)for applications is not guaranteed.By using a device driver,which is running in kernel mode,the real time performance of Windows can be enhanced greatly.The acknowledgment performance of Windows to peripheral interrupts was evaluated.Harmonized with an intelligent real-time serial communication bus(RTSB),strict real-time performance can be achieved in Windows platform.An opened architecture software CNC system which is hardware independence is proposed based on PC and RTSB.A numerical control real time kernel(NCRTK),which is implemented as a device driver on Windows,is used to perform the NC tasks.Tasks are divided into real-time and non real-time.Real-time task is running in kernel mode and non real-time task is running in user mode.Data are exchanged between kernel and user mode by DMA and Windows Messages.展开更多
This pilot study focuses on a real measurements and enhancements of a software defined radio-based system for vehicle-to everything visible light communication(SDR-V2X-VLC).The presented system is based on a novel ada...This pilot study focuses on a real measurements and enhancements of a software defined radio-based system for vehicle-to everything visible light communication(SDR-V2X-VLC).The presented system is based on a novel adaptive optimization of the feed-forward software defined equalization(FFSDE)methods of the least mean squares(LMS),normalized LMS(NLMS)and QR decomposition-based recursive least squares(QR-RLS)algorithms.Individual parameters of adaptive equalizations are adjusted in real-time to reach the best possible results.Experiments were carried out on a conventional LED Octavia III taillight drafted directly from production line and universal software radio peripherals(USRP)from National Instruments.The transmitting/receiving elements used multistate quadrature amplitude modulation(M-QAM)implemented in LabVIEW programming environment.Experimental results were verified based on bit error ratio(BER),error vector magnitude(EVM)and modulation error ratio(MER).Experimental results of the pilot study unambiguously confirmed the effectiveness of the proposed solution(longer effective communication range,higher immunity to interference,deployment of higher state QAM modulation formats,higher transmission speeds etc.),as the adaptive equalization significantly improved BER,MER and EVM parameters.The best results were achieved using the QR-RLS algorithm.The results measured on deployed QR-RLS algorithm had significantly better Eb/N0(improved by approx.20 dB)and BER values(difference by up to two orders of magnitude).展开更多
基金Supported by the National Natural Science Foundation of China(No.61179045 and No.61350009)
文摘In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.
基金Supported by the National Natural Science Foundation of China(11301255)the Fund by Collaborative Innovation Center of IoT Industrialization and Intelligent Production,Minjiang University(IIC1703)+1 种基金Foundation of Minjiang University(MYK17032)the Program for New Century Excellent Talents in Fujian Province University
文摘Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is further converted equivalently to an unconstrained binary integer programming problem by a penalty method. A local search method, HSFM, is developed to obtain a discrete local minimizer of the unconstrained binary integer programming problem. Next, an auxiliary function, which has the same global optimal solutions as the unconstrained binary integer programming problem, is constructed, and its properties are studied. We show that applying HSFM to minimize the auxiliary function can escape from previous local optima by the increase of the parameter value successfully. Finally, a discrete dynamic convexized method is developed to solve the hardware/software partitioning problem. Computational results and comparisons indicate that the proposed algorithm can get high-quality solutions.
文摘Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.
基金Sponsored by the Natural Science Foundation of Heilongjiang Province( Grant No B2007-07)Industrial Research Projects in Qiqihaer( Grant No GYGG-09009)
文摘This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.
基金Project supported by the Key-Tech Program of Zhejiang Province,China (No. 021101559), and the Fok Ying Tong Education Founda-tion (No. 94031), China
文摘In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.
文摘This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.
文摘With the rapid development of information technology in the energy industry, the use of information means to integrate and share all kinds of resources, to improve the utilization rate of resources, to achieve the purposes of rational use of resources, cost reduction and efficiency improvement, and to improve the labor efficiency has become the primary task of oilfield information and scientific research management. This paper mainly discusses the application of "enterprise-class professional software and hardware cloud" in scientific research, and mainly discusses the contents of professional software and hardware sharing application, intelligent operation and maintenance, data sharing, remote collaboration, etc., and organically combines information management with scientific research and production management, thus effectively improving the management level of scientific research software and hardware.
文摘With the progress of the times and the development of information technology, the computer has become a life tool. Due to its intelligent convenience, it is widely used in daily life, but the inevitable failure problems of the machine, or the loss of the computer and data, and causes immeasurable trouble and loss.
文摘We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.
文摘The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.
文摘The dual-motor controller system is one of the key components in the multi-power architecture of new energy vehicles and is crucial to the safe operation of the vehicle.From the perspective of functional safety,this article takes the torque safety goal of"avoiding unexpected acceleration of the vehicle due to unexpected acceleration torque"as an example to explore various software and hardware architecture implementation methods,and analysis the test scheme covering multiple stages such as HIL/PowerHIL testing,bench testing and vehicle testing to verify the effectiveness of the safety path.Through the verification of the safety strategy,it provides innovative ideas for the functional safety design and testing of the electric drive control system,which is expected to provide a reference for improving the overall safety of new energy vehicles.
基金supported by National Science and Technology Major Project granted No.2016ZX01012101
文摘With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.
基金Science and Technology on Avionics Integration Laboratory and Aeronautical Science Foundation of China (20115551022)
文摘This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.
基金financial support of National Natural Science Foundation of China(NSFC),No.U1705263 and 61971102GF Innovative Research Programthe Sichuan Science and Technology Program,No.2019YJ0194。
文摘In order to satisfy the ever-increasing energy appetite of the massive battery-powered and batteryless communication devices,radio frequency(RF)signals have been relied upon for transferring wireless power to them.The joint coordination of wireless power transfer(WPT)and wireless information transfer(WIT)yields simultaneous wireless information and power transfer(SWIPT)as well as data and energy integrated communication network(DEIN).However,as a promising technique,few efforts are invested in the hardware implementation of DEIN.In order to make DEIN a reality,this paper focuses on hardware implementation of a DEIN.It firstly provides a brief tutorial on SWIPT,while summarising the latest hardware design of WPT transceiver and the existing commercial solutions.Then,a prototype design in DEIN with full protocol stack is elaborated,followed by its performance evaluation.
文摘This paper introduces an effective software-based FEC redundant packets generating algorithm. The algorithm is based on Reed-Solomon coding over Galois Field. By operating on words of packets and performing polynomial multiplication via lookup tables, software coding efficiency is achieved to satisfy the needs of most of computer network applications. The approach to generate lookup tables is detailed.
基金the Aeronautics Science Foundation of China(No.2011ZD51055)Science and Technology on Reliability&Environmental Engineering Laboratory(No.302367)the National Pre-Research Foundation of China(No.51319080201)
文摘Robustness testing for safety-critical embedded software is still a challenge in its nascent stages. In this paper, we propose a practical methodology and implement an environment by employing model-based robustness testing for embedded software systems. It is a system-level black-box testing approach in which the fault behaviors of embedded software is triggered with the aid of modelbased fault injection by the support of an executable model-driven hardware-in-loop （HIL） testing environment. The prototype implementation of the robustness testing environment based on the proposed approach is experimentally discussed and illustrated by industrial case studies based on several avionics-embedded software systems. The results show that our proposed and implemented robustness testing method and environment are effective to find more bugs, and reduce burdens of testing engineers to enhance efficiency of testing tasks, especially for testing complex embedded systems.
基金funding from the German Federal Ministry for Education and Research(2015-2017)under the grant agreement No.16KIS0179 also referred as DEAL
文摘In this paper, a novel Medium Access Control (MAC) protocol for industrial Wireless Local Area Networks (WLANs) is proposed and studied. The main challenge in industry automation systems is the ultra-low network latency with a target upper bound in the order of 1 ms while maintaining high network reliability and availability. The novelty of the proposed wireless MAC protocol resides in its similar latency performance as its counterpart in wired industrial LAN. First, the functional design of the MAC protocol is introduced. Then its performance results gained from hardware implementation (SystemC and VHDL) on an FPGA platform are presented. Finally, a real-time communication module which achieves the ultra-low latency required in industrial automation is described.
基金supported by the National Key Research and Development Program of China(Nos.2017YFC1403403,2017YFC1403304)。
文摘In this study,a mathematical model of multipath channels is established,and the delay parameters of 10-path models are calculated at 300 m.A multipath-channel hardware simulator based on a field programmable gate array(FPGA)is designed and verified at 100 k Hz,200 k Hz,500 k Hz,1 MHz,and 24 MHz transmission frequencies.According to the characteristics of the ocean induction coupling chain channel,the orthogonal frequency-division multiplexing(OFDM)algorithm parameters are designed by referring to the wireless communication protocol.The appropriate length cyclic prefix(CP)is added in the OFDM symbol to resist the multipath effect of the seawater channel,and the FPGA hardware transceiver based on the OFDM algorithm is realized.The hardware platform of the ocean induction coupling chain communication system is developed to resist the multipath effect of the seawater channel and tested at 24 MHz.The experimental results show that 800 ns is the best CP length for the developed system,which can effectively resist the multipath effect,with a signal-to-noise ratio above 24 d B and a bit error rate below 1%.This study provides a hardware simulation test platform and an effective method to resist the multipath effect of a seawater channel and improve the transmission performance of the seawater channel.
基金Supported by the National Natural Science Foundation of China(No.50445004).
文摘Computer numerical control(CNC)system is the base of modern digital and intelligent manufacturing technolo-gy.And opened its architecture and constituted based on PC and Windows operating system(OS)is the main trend of CNC sys-tem.However,even if the highest system priority is used in user mode,real-time capability of Windows(2000,NT,XP)for applications is not guaranteed.By using a device driver,which is running in kernel mode,the real time performance of Windows can be enhanced greatly.The acknowledgment performance of Windows to peripheral interrupts was evaluated.Harmonized with an intelligent real-time serial communication bus(RTSB),strict real-time performance can be achieved in Windows platform.An opened architecture software CNC system which is hardware independence is proposed based on PC and RTSB.A numerical control real time kernel(NCRTK),which is implemented as a device driver on Windows,is used to perform the NC tasks.Tasks are divided into real-time and non real-time.Real-time task is running in kernel mode and non real-time task is running in user mode.Data are exchanged between kernel and user mode by DMA and Windows Messages.
基金This research was funded by the European Regional Development Fund in the Research Centre of Advanced Mechatronic Systems project,Project Number CZ.02.1.01/0.0/0.0/16_019/0000867 and by 543 the Ministry of Education of the Czech Republic,Project No.SP2021/32.
文摘This pilot study focuses on a real measurements and enhancements of a software defined radio-based system for vehicle-to everything visible light communication(SDR-V2X-VLC).The presented system is based on a novel adaptive optimization of the feed-forward software defined equalization(FFSDE)methods of the least mean squares(LMS),normalized LMS(NLMS)and QR decomposition-based recursive least squares(QR-RLS)algorithms.Individual parameters of adaptive equalizations are adjusted in real-time to reach the best possible results.Experiments were carried out on a conventional LED Octavia III taillight drafted directly from production line and universal software radio peripherals(USRP)from National Instruments.The transmitting/receiving elements used multistate quadrature amplitude modulation(M-QAM)implemented in LabVIEW programming environment.Experimental results were verified based on bit error ratio(BER),error vector magnitude(EVM)and modulation error ratio(MER).Experimental results of the pilot study unambiguously confirmed the effectiveness of the proposed solution(longer effective communication range,higher immunity to interference,deployment of higher state QAM modulation formats,higher transmission speeds etc.),as the adaptive equalization significantly improved BER,MER and EVM parameters.The best results were achieved using the QR-RLS algorithm.The results measured on deployed QR-RLS algorithm had significantly better Eb/N0(improved by approx.20 dB)and BER values(difference by up to two orders of magnitude).
