This paper presents a new encryption embedded processor aimed at the application requirement of wireless sensor network （WSN）. The new encryption embedded processor not only offers Rivest Shamir Adlemen （RSA）, Adv...This paper presents a new encryption embedded processor aimed at the application requirement of wireless sensor network （WSN）. The new encryption embedded processor not only offers Rivest Shamir Adlemen （RSA）, Advanced Encryption Standard （AES）, 3 Data Encryption Standard （3 DES） and Secure Hash Algorithm 1 （SHA - 1 ） security engines, but also involves a new memory encryption scheme. The new memory encryption scheme is implemented by a memory encryption cache （MEC）, which protects the confidentiality of the memory by AES encryption. The experi- ments show that the new secure design only causes 1.9% additional delay on the critical path and cuts 25.7% power consumption when the processor writes data back. The new processor balances the performance overhead, the power consumption and the security and fully meets the wireless sensor environment requirement. After physical design, the new encryption embedded processor has been successfully tape-out.展开更多
When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other...When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.展开更多
针对由周期任务和零星任务形成的实时混合任务集进行合理调度问题,文中提出了一种基于零松弛度边界公平(Boundary Fair until Zero Laxity,BFZL)的实时混合任务算法。该算法在改进边界公平(Improved Boundary Fair,I-BF)实时混合任务算...针对由周期任务和零星任务形成的实时混合任务集进行合理调度问题,文中提出了一种基于零松弛度边界公平(Boundary Fair until Zero Laxity,BFZL)的实时混合任务算法。该算法在改进边界公平(Improved Boundary Fair,I-BF)实时混合任务算法基础上,通过引入最小松弛度优先(Least Laxity First,LLF)算法中的松弛度参数来改进判定任务的优先级,并提出基于松弛度与启发式策略相结合的启发式算法改进任务的分配策略。实验结果表明,BFZL算法能够满足系统实时性,并达到了算法优化目的。通过数据对比分析可知,该算法相比于原始算法,零星任务的平均响应时间降低了约26%,上下文切换减少了约28%,迁移减少了约50%。该算法在调度开销方面也具有一定优势。展开更多
Embedded and Internet of Things(IoT)devices have extremely strict requirements on the area and power consumption of the processor because of the limitation on its working environment.To reduce the overhead of the embe...Embedded and Internet of Things(IoT)devices have extremely strict requirements on the area and power consumption of the processor because of the limitation on its working environment.To reduce the overhead of the embedded processor as much as possible,this paper designs and implements a configurable 32-bit in-order RISC-V processor core based on the 16-bit data path and units,named RV16.The evaluation results show that,compared with the traditional 32-bit RISC-V processor with similar features,RV16 consumes fewer hardware resources and less power consumption.The maximum performance of RV16 running Dhrystone and CoreMark benchmarks is 0.92 DMIPS/MHz and 1.51 CoreMark/MHz,respectively,reaching 75%and 71%of traditional 32-bit processors,respectively.Moreover,a properly configured RV16 running program also consumes less energy than a traditional 32-bit processor.展开更多
Application of embedded systems is faced with multiple threats against security. To solve this problem, this article proposes a new program memory encryption mechanism （PEM） to enhance the security of embedded proce...Application of embedded systems is faced with multiple threats against security. To solve this problem, this article proposes a new program memory encryption mechanism （PEM） to enhance the security of embedded processor. The new mechanism encrypts all the programs via a secure cache structure. It not only caches the instructions read from the off-chip memory, but also stores the pad values used to encrypt the plaintext. It effectively accelerates encryption and reduces the performance overhead. Besides the encryption, PEM also monitors the program modifications and reset behaviors to reduce the risk of vicious tamper. The experiment indicates that PEM has an average of 2.3 % performance improvement and results in a 25.71% power reduction in the write-back stage. The new scheme offers a good balance between performance and security. It is fully practicable for embedded processor.展开更多
To enhance the computational density and energy efficiency of on-chip neuromorphic hardware,this study introduces a novel network architecture for multi-task processing with in-memory optical computing.On-chip optical...To enhance the computational density and energy efficiency of on-chip neuromorphic hardware,this study introduces a novel network architecture for multi-task processing with in-memory optical computing.On-chip optical neural networks are celebrated for their capability to transduce a substantial volume of parameters into optical form while conducting passive computing,yet they encounter challenges in scalability and multitasking.Leveraging the principles of transfer learning,this approach involves embedding the majority of parameters into fixed optical components and a minority into adjustable electrical components.Furthermore,with deep regression algorithm in modeling physical propagation process,a compact optical neural network achieve to handle diverse tasks.In this work,two ultra-compact in-memory diffraction-based chips with integration of more than 60,000 parameters/mm^(2) were fabricated,employing deep neural network model and the hard parameter sharing algorithm,to perform multifaceted classification and regression tasks,respectively.The experimental results demonstrate that these chips achieve accuracies comparable to those of electrical networks while significantly reducing the power-intensive digital computation by 90%.Our work heralds strong potential for advancing in-memory optical computing frameworks and next generation of artificial intelligence platforms.展开更多
文摘This paper presents a new encryption embedded processor aimed at the application requirement of wireless sensor network （WSN）. The new encryption embedded processor not only offers Rivest Shamir Adlemen （RSA）, Advanced Encryption Standard （AES）, 3 Data Encryption Standard （3 DES） and Secure Hash Algorithm 1 （SHA - 1 ） security engines, but also involves a new memory encryption scheme. The new memory encryption scheme is implemented by a memory encryption cache （MEC）, which protects the confidentiality of the memory by AES encryption. The experi- ments show that the new secure design only causes 1.9% additional delay on the critical path and cuts 25.7% power consumption when the processor writes data back. The new processor balances the performance overhead, the power consumption and the security and fully meets the wireless sensor environment requirement. After physical design, the new encryption embedded processor has been successfully tape-out.
文摘When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.
文摘针对由周期任务和零星任务形成的实时混合任务集进行合理调度问题,文中提出了一种基于零松弛度边界公平(Boundary Fair until Zero Laxity,BFZL)的实时混合任务算法。该算法在改进边界公平(Improved Boundary Fair,I-BF)实时混合任务算法基础上,通过引入最小松弛度优先(Least Laxity First,LLF)算法中的松弛度参数来改进判定任务的优先级,并提出基于松弛度与启发式策略相结合的启发式算法改进任务的分配策略。实验结果表明,BFZL算法能够满足系统实时性,并达到了算法优化目的。通过数据对比分析可知,该算法相比于原始算法,零星任务的平均响应时间降低了约26%,上下文切换减少了约28%,迁移减少了约50%。该算法在调度开销方面也具有一定优势。
基金the National Key Research and Development Project of China under Grant No.2021YFB0300300the National Natural Science Foundation of China under Grant Nos.62090023,61872374,61672526 and 62172430the Natural Science Foundation of Hunan Province of China under Grant No.2021JJ10052.
文摘Embedded and Internet of Things(IoT)devices have extremely strict requirements on the area and power consumption of the processor because of the limitation on its working environment.To reduce the overhead of the embedded processor as much as possible,this paper designs and implements a configurable 32-bit in-order RISC-V processor core based on the 16-bit data path and units,named RV16.The evaluation results show that,compared with the traditional 32-bit RISC-V processor with similar features,RV16 consumes fewer hardware resources and less power consumption.The maximum performance of RV16 running Dhrystone and CoreMark benchmarks is 0.92 DMIPS/MHz and 1.51 CoreMark/MHz,respectively,reaching 75%and 71%of traditional 32-bit processors,respectively.Moreover,a properly configured RV16 running program also consumes less energy than a traditional 32-bit processor.
基金supported by the National Natural Science Foundation of China (60973034)the Program for New Century Excellent Talents in University (NCET-07-0328)
文摘Application of embedded systems is faced with multiple threats against security. To solve this problem, this article proposes a new program memory encryption mechanism （PEM） to enhance the security of embedded processor. The new mechanism encrypts all the programs via a secure cache structure. It not only caches the instructions read from the off-chip memory, but also stores the pad values used to encrypt the plaintext. It effectively accelerates encryption and reduces the performance overhead. Besides the encryption, PEM also monitors the program modifications and reset behaviors to reduce the risk of vicious tamper. The experiment indicates that PEM has an average of 2.3 % performance improvement and results in a 25.71% power reduction in the write-back stage. The new scheme offers a good balance between performance and security. It is fully practicable for embedded processor.
基金supported by the National Key R&D Plan of China(2024YFE0203600)the National Natural Science Foundation of China(62135009).
文摘To enhance the computational density and energy efficiency of on-chip neuromorphic hardware,this study introduces a novel network architecture for multi-task processing with in-memory optical computing.On-chip optical neural networks are celebrated for their capability to transduce a substantial volume of parameters into optical form while conducting passive computing,yet they encounter challenges in scalability and multitasking.Leveraging the principles of transfer learning,this approach involves embedding the majority of parameters into fixed optical components and a minority into adjustable electrical components.Furthermore,with deep regression algorithm in modeling physical propagation process,a compact optical neural network achieve to handle diverse tasks.In this work,two ultra-compact in-memory diffraction-based chips with integration of more than 60,000 parameters/mm^(2) were fabricated,employing deep neural network model and the hard parameter sharing algorithm,to perform multifaceted classification and regression tasks,respectively.The experimental results demonstrate that these chips achieve accuracies comparable to those of electrical networks while significantly reducing the power-intensive digital computation by 90%.Our work heralds strong potential for advancing in-memory optical computing frameworks and next generation of artificial intelligence platforms.
