Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchro...Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchronous reference frame phase-locked loop(SRF-PLL)plays a critical role in grid synchronization for renewable power generation.However,there is a notable research gap regarding the application of FOC to the SRF-PLL.This paper proposes a fractional-order SRF-PLL(FO-SRF-PLL)that incorporates FOC to accurately track the phase angle of the terminal voltage,thereby improving the efficiency of grid-connected control.The dynamic performance of the proposed FO-SRF-PLL is evaluated under varying grid conditions.A comprehensive analysis of the small-signal stability of the GCC system employing the FO-SRF-PLL is also presented,including derived small-signal stability conditions.The results demonstrate that the FO-SRF-PLL significantly enhances robustness against disturbances compared with the conventional SRF-PLL.Furthermore,the GCC system with the FO-SRF-PLL maintains stability even under weak grid conditions,showing superior stability performance over the SRF-PLL.Finally,both simulation and experimental results are provided to validate the analysis and conclusions presented in this paper.展开更多
A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs...A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.展开更多
基金supported in part by the Natural Science Foundation of China(No.52077144)the Youth Innovative Research Team of Science and Technology Scheme,Sichuan Province,China(No.22CXTD0066).
文摘Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchronous reference frame phase-locked loop(SRF-PLL)plays a critical role in grid synchronization for renewable power generation.However,there is a notable research gap regarding the application of FOC to the SRF-PLL.This paper proposes a fractional-order SRF-PLL(FO-SRF-PLL)that incorporates FOC to accurately track the phase angle of the terminal voltage,thereby improving the efficiency of grid-connected control.The dynamic performance of the proposed FO-SRF-PLL is evaluated under varying grid conditions.A comprehensive analysis of the small-signal stability of the GCC system employing the FO-SRF-PLL is also presented,including derived small-signal stability conditions.The results demonstrate that the FO-SRF-PLL significantly enhances robustness against disturbances compared with the conventional SRF-PLL.Furthermore,the GCC system with the FO-SRF-PLL maintains stability even under weak grid conditions,showing superior stability performance over the SRF-PLL.Finally,both simulation and experimental results are provided to validate the analysis and conclusions presented in this paper.
基金Project supported by the National Natural Science Foundation of China(No.61176029)the National Twelve-Five Project(No.513***)
文摘A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.
