Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic...Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.展开更多
A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device....A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.展开更多
Persistent luminescence has emerged as a robust platform for anti-counterfeiting applications due to its exceptional spatial-temporal decoding capability.Yet,conventional strategies often suffer from uniform emission ...Persistent luminescence has emerged as a robust platform for anti-counterfeiting applications due to its exceptional spatial-temporal decoding capability.Yet,conventional strategies often suffer from uniform emission patterns and predictable replication,compromising their security.Herein,we present“Snap-PLNPs”—near-infrared emitting CaS:Tm persistent luminescent nanoparticles engineered to undergo aqueous-triggered self-destruction via a hydrolysis mechanism.In contrast to traditional photophysical approaches,this chemically initiated degradation irreversibly terminates the luminescence,ensuring that security information can be decoded only once.Moreover,by incorporating an additional SiO_(2)shell,we introduce a programmable delay in the hydrolysis process,thereby modulating the duration of the emission and adding a temporal regulation layer.This dual control—combining instantaneous chemical deactivation with time-resolved modulation—establishes a dynamic hierarchical security encoding framework.When embedded into laser-engraved logos,these CaS:Tm@SiO_(2)hybrids enable a novel triple-layer anti-counterfeiting strategy that integrates spatial,temporal,and chemical dimensions.Our results underscore the potential of Snap-PLNPs as a next-generation platform for robust and adaptive security technologies.展开更多
基金supported by the National Natural Science Foundation of China(61401204)the Fundamental Research Funds for the Central Universities(30916011319)+1 种基金the Technology Research and Development Program of Jiangsu Province(BY2015004-03)the Postdoctoral Science Foundation of Jiangsu Province(1501104C)
文摘Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.
基金Supported by the National High Technology Research and Development Program(No.2012AA121901)
文摘A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.
基金supported by the National Natural Science Foundation of China(Grant No.52172083)Zhejiang Province Key R&D Program:Vanguard and Leading Geese Projects(Grant No.2024C01190)+1 种基金the Guangzhou Key Research and Development Program(Grant No.2023B03J1239)Program for Innovative Research Team in University of Education System of Guangzhou(Grant No.202235404).
文摘Persistent luminescence has emerged as a robust platform for anti-counterfeiting applications due to its exceptional spatial-temporal decoding capability.Yet,conventional strategies often suffer from uniform emission patterns and predictable replication,compromising their security.Herein,we present“Snap-PLNPs”—near-infrared emitting CaS:Tm persistent luminescent nanoparticles engineered to undergo aqueous-triggered self-destruction via a hydrolysis mechanism.In contrast to traditional photophysical approaches,this chemically initiated degradation irreversibly terminates the luminescence,ensuring that security information can be decoded only once.Moreover,by incorporating an additional SiO_(2)shell,we introduce a programmable delay in the hydrolysis process,thereby modulating the duration of the emission and adding a temporal regulation layer.This dual control—combining instantaneous chemical deactivation with time-resolved modulation—establishes a dynamic hierarchical security encoding framework.When embedded into laser-engraved logos,these CaS:Tm@SiO_(2)hybrids enable a novel triple-layer anti-counterfeiting strategy that integrates spatial,temporal,and chemical dimensions.Our results underscore the potential of Snap-PLNPs as a next-generation platform for robust and adaptive security technologies.
