The design of a pixel processor of a real-time CIG (Computer Image Generation) system is summarized. The system has been brought into use. In order to adopt ASIC (Application-Specific integrated Circuit) technology in...The design of a pixel processor of a real-time CIG (Computer Image Generation) system is summarized. The system has been brought into use. In order to adopt ASIC (Application-Specific integrated Circuit) technology in the design of the new system, the VHDL (Very high speed integrated circuit Hardware Description Language) is used and a re-design and simulation strategy is planed.展开更多
针对高效视频编码(high efficiency video coding,HEVC)分像素运动估计亮度分量插值算法计算量大、冗余度高、难以实现不同编码块之间灵活切换的问题,提出一种动态可重构且具有高数据复用率的分像素插值算法实现方法。根据编码单元(codi...针对高效视频编码(high efficiency video coding,HEVC)分像素运动估计亮度分量插值算法计算量大、冗余度高、难以实现不同编码块之间灵活切换的问题,提出一种动态可重构且具有高数据复用率的分像素插值算法实现方法。根据编码单元(coding unit,CU)的规模和大小自适应地对其周围参考像素块进行插值计算,得到最优预测单元的编码模式和运动矢量。实验结果表明,与专用硬件实现的分像素插值算法相比,不同编码块灵活切换的同时,参考像素的读取数量减少43.8%,硬件资源消耗减少18.5%。展开更多
文摘The design of a pixel processor of a real-time CIG (Computer Image Generation) system is summarized. The system has been brought into use. In order to adopt ASIC (Application-Specific integrated Circuit) technology in the design of the new system, the VHDL (Very high speed integrated circuit Hardware Description Language) is used and a re-design and simulation strategy is planed.
文摘针对高效视频编码(high efficiency video coding,HEVC)分像素运动估计亮度分量插值算法计算量大、冗余度高、难以实现不同编码块之间灵活切换的问题,提出一种动态可重构且具有高数据复用率的分像素插值算法实现方法。根据编码单元(coding unit,CU)的规模和大小自适应地对其周围参考像素块进行插值计算,得到最优预测单元的编码模式和运动矢量。实验结果表明,与专用硬件实现的分像素插值算法相比,不同编码块灵活切换的同时,参考像素的读取数量减少43.8%,硬件资源消耗减少18.5%。
