Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noi...Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noises and torque ripples.This article proposes an enhanced model-based sensorless approach to extend downwards the speed range in which sensorless control can work without injection.An inertial phase-locked loop (IPLL) based on a stator flux observer is introduced for position estimation.Compared to the conventional phase-locked loop scheme,the IPLL offers a more robust disturbance rejection capability and thus reduces the flux model errors at lower speeds.Experimental results substantiate the feasibility of the extended low-speed operation using the model-based sensorless control approach.展开更多
We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics...We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics collimator（AFOC）,and the PL control is realized by the phase modulator（PM）.Cascaded and simultaneous controls of TT and PL using stochastic parallel gradient descent（SPGD） algorithm are investigated in this paper.Two-fiber-laser-,four-fiber-laser-,and six-fiber-laser-arrays are employed to study the TT and PL control.In the cascaded control system,only one high-speed CMOS camera is used to collect beam data and a computer is used as the controller.In a simultaneous control system one high-speed CMOS camera and one photonic detector（PD） are employed,and a computer and a control circuit based on field programmable gate array（FPGA） are used as the controllers.Experimental results reveal that both cascaded and simultaneous controls of TT using AFOC and PL using PM in fiber laser array are feasible and effective.Cascaded control is more effective in static control situation and simultaneous control can be applied to the dynamic control system directly.The control signals of simultaneous PL and TT disturb each other obviously and TT and PL control may compete with each other,so the control effect is limited.展开更多
In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for...In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.展开更多
In this paper,a sensorless control strategy of a permanent magnet synchronous machine(PMSM)based on an improved rotor flux observer(IFO)is proposed.Due to the unknown integral initial value and the high harmonics caus...In this paper,a sensorless control strategy of a permanent magnet synchronous machine(PMSM)based on an improved rotor flux observer(IFO)is proposed.Due to the unknown integral initial value and the high harmonics caused by current sampling and inverter nonlinearities,the flux linkage estimated by traditional rotor flux observer may be inaccurate.In order to address these issues,a self-adaptive band-pass filter(SABPF)is designed to eliminate the DC component and high-frequency harmonics of the estimated equivalent rotor flux linkage.Furthermore,in order to avoid that the design of PI parameter is influenced by the amplitude of equivalent rotor flux linkage,an improved phase-locked loop(IPLL)is employed to obtain the rotor speed and to normalize the estimated equivalent rotor flux linkage.In addition,angle shift caused by an SABPF is compensated to improve the accuracy of the estimated flux linkage angle.Besides,the parameter robustness of this method is analyzed in detail.Finally,simulation and experimental results demonstrate the effectiveness and parameter robustness of the proposed method.展开更多
In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is c...In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is controlled by a 16-bit single chip microprocessor.A new type of frequency and phase detector is presented in detail,An adaptive method isadopted in speed controller.A three mode control scheme is used.These techniques are very use-ful to the improvement of the dynamic behavior of digital AC motor drive system.Experimental results show that the system is of good stability,high precision and good dynam-ic performance.展开更多
A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works...A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.展开更多
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac...A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.展开更多
A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel...A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.展开更多
Most permanent magnet synchronous generator(PMSG)based wind generation systems currently employ grid-following control,relying on a phase-locked loop(PLL)for grid connection.However,it leads to a lack of inertia suppo...Most permanent magnet synchronous generator(PMSG)based wind generation systems currently employ grid-following control,relying on a phase-locked loop(PLL)for grid connection.However,it leads to a lack of inertia support in the system.To address this,the virtual inertia control(VIC)is crucial for improvement,yet it introduces potential instability due to torsional oscillation interaction with PLL and low-frequency oscillations,which is an underexplored area.This paper presents a comprehensive analysis of the grid-connected PMSG-based wind generation system.It confirms the necessity of employing a full-order model for studying stability on the quasi-electromechanical timescale(QET)by a comparison with the reduced-order model.Then,a comprehensive modal analysis is conducted to analyze the effect of VIC parameters,shaft inertia time constant,PLL parameters,and torsional oscillation damping(TOD)controller gain on the interaction of QET oscillations under two typical control strategies.The occurrence of interaction and mode conversion is observed when the oscillation frequency and root loci of the torsional,PLL,and low-frequency oscillations are close.Finally,a theoretical analysis is validated via simulation verification in Simulink.These findings offer a valuable guidance for industrial PMSG applications considering VIC.展开更多
When the power grid suffers from grid faults that cause phase disturbances,the grid-connected converter becomes destabilized by the interaction between the phase-locked loop(PLL)and the control loop.In this paper,the ...When the power grid suffers from grid faults that cause phase disturbances,the grid-connected converter becomes destabilized by the interaction between the phase-locked loop(PLL)and the control loop.In this paper,the stability of the PLL affected by the control loop under transient grid faults is studied.First,the equivalent model of the PLL under the influence of the control loop is established.Then,different response processes of PLLs under the ground fault with various control parameters are qualitatively analyzed.Furthermore,a small-signal model is proposed to assess the stability of the PLL under different control loop parameters.The system poles can be calculated to show the physical origin of the instability.Finally,simulations of a three-phase 21-level modular multilevel converter(MMC)built in PSCAD and a down-scale experiment is performed to verify the parameter influence of the control loop on the PLL.展开更多
An optical phase locking method based on direct phase control is proposed.The core of this method is to synchronize the carrier by directly changing the phase of the local beam.The corresponding experimental device an...An optical phase locking method based on direct phase control is proposed.The core of this method is to synchronize the carrier by directly changing the phase of the local beam.The corresponding experimental device and the supporting algorithm were configured to verify the feasibility of this method.Phase locking can be completed without cycle skipping,and the acquisition time is 530 ns.Without an optical preamplifier,a sensitivity of-34.4 d Bm is obtained,and the bit error rate is 10^(-9) for 2.5 Gbit/s binary phase-shift keying modulation.The measured standard deviation of the phase error is 5.2805°.展开更多
A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which a...A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.展开更多
Increasing penetration of power electronic(PE)grid-tied devices has caused more and more dynamic problems with unknown mechanisms.Since grid operation asks for a certain voltage amplitude and frequency level when ther...Increasing penetration of power electronic(PE)grid-tied devices has caused more and more dynamic problems with unknown mechanisms.Since grid operation asks for a certain voltage amplitude and frequency level when there is a power imbalance,roles of the PE grid-tied devices during dynamics must be characterized as internal voltage response under power excitation,in which the voltage vector evolves through its timevarying amplitude and frequency.Existing modeling works,unfortunately,fail to recognize amplitude and frequency modulation essence of grid voltage during dynamics,so corresponding linear models are inapplicable to small-perturbation grid dynamic analysis.Thus,taking current control timescale of grid-tied voltage source converter(VSC)for example,this paper establishes a model with active and reactive current excitation and internal voltage amplitude and frequency response.Especially,the role of the terminal voltage detection-based phase-locked loop(PLL)in the excitation-response relationship is revealed.Linearization is conducted by clarifying amplitude and frequency operating points and corresponding increments of AC signals.This model intuitively reflects the evolution of internal voltage amplitude and frequency excited by active and reactive currents,which represents characteristics of the device during dynamics.Then,simulations for verification of the linear model and time-varying nature of amplitude and frequency are presented.Features of the characteristics of VSC are preliminarily discussed.展开更多
This study examines whether power systems using 100%phase-locked loop(PLL)-synchronized voltage-source converters(VSCs)can operate independently.While grid-forming(GFM)technology lacks a unified definition,independent...This study examines whether power systems using 100%phase-locked loop(PLL)-synchronized voltage-source converters(VSCs)can operate independently.While grid-forming(GFM)technology lacks a unified definition,independent operation remains its core requirement.Current views incorrectly associate PLL synchronization solely with grid-following(GFL)control,assuming that PLL-based equipment requires support from synchronous generators or GFM devices.We challenge this by revealing three essential conditions for independent operation in fully PLL-synchronized systems:stable device synchronization,controllable node voltages,and adjustable system frequency.Through detailed analysis and tests,we prove these requirements can be met in 100%VSC systems using PLL synchronization.This discovery breaks the traditional link between operational independence and synchronization methods.Our findings offer new insights for developing renewable-dominated grids.The above three conditions have been proven to be achievable in a 100%PLL-synchronized VSC system.展开更多
The negative-sequence voltage is often caused by the asymmetrical fault in the AC system,as well as the harmonics after the symmetrical fault at the AC side of inverter in line commutated converter based high-voltage ...The negative-sequence voltage is often caused by the asymmetrical fault in the AC system,as well as the harmonics after the symmetrical fault at the AC side of inverter in line commutated converter based high-voltage DC(LCC-HVDC).The negative-sequence voltage affects the phase-locked loop(PLL)and the inverter control,thus the inverter is vulnerable to the subsequent commutation failure(SCF).In this paper,the analytical expression of the negative-sequence voltage resulting from the symmetrical fault with the commutation voltage is derived using the switching function and Fourier decomposition.The analytical expressions of the outputs of the PLL and inverter control with respect to time are derived to quantify the contribution of the negative-sequence voltage to the SCF.To deal with the AC component of the input signals in the PLL and the inverter control due to the negative-sequence voltage,the existing proportional-integral controls of the PLL,constant current control,and constant extinction angle control are replaced by the linear active disturbance rejection control against the SCF.Simulation results verify the contributing factors to the SCF.The proposed control reduces the risk of SCF and improves the recovery speed of the system under different fault conditions.展开更多
This letter studies large-disturbance stability of the power system with a synchronous generator(SG)and a converter-interfaced generation(CIG)connected to infinite bus.The power system is multi-timescale and first sim...This letter studies large-disturbance stability of the power system with a synchronous generator(SG)and a converter-interfaced generation(CIG)connected to infinite bus.The power system is multi-timescale and first simplified.It is shown that the boundary of region of attraction(ROA)of the simplified model is composed of stable manifolds of unstable equilibrium point(UEP)or semi-singular point(SSP),named anchor points,and singular surface pieces.The type of anchor point determines the dominant instability pattern of the power system.When the anchor point is UEP or SSP,the dominant instability pattern is the instability of rotor angle of SG or the instability of phase-locked loop and outer control loop(OCL)of CIG,respectively.Transition of dominant instability pattern can be analyzed with the relative position relationship between UEP and SSP.The effect of OCL is discussed.When the OCL is activated,the ROA becomes smaller and the system is more prone to instability of CIG.It is necessary to consider the OCL when studying the large-disturbance stability of the power system.展开更多
A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the ...A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.展开更多
A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks o...A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector（PFD）,and a new feedback structure is utilized in the charge pump（CP） for ultra-low voltage applications.The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power.In addition,several novel design techniques,such as removing the tail current source,are demonstrated to cut down the phase noise.Implemented in the SMIC 0.13μm RF CMOS process and operated at 0.8 V supply voltage,the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz.The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply.The occupied chip area of the PFD and CP is 100×100μm^2.The chip occupies 0.63 mm^2,and draws less than 6.54 mW from a 0.8 V supply.展开更多
基金supported in part by the National Natural Science Foundation of China 52307069in part by 2024 Tertiary Education Scientific Research Project of Guangzhou Municipal Education Bureau under Grant2024312176in part by the Project of Hetao Shenzhen-Hong Kong Science and Technology Innovation Cooperation Zone under Grant HZQB-KCZYB-2020083。
文摘Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noises and torque ripples.This article proposes an enhanced model-based sensorless approach to extend downwards the speed range in which sensorless control can work without injection.An inertial phase-locked loop (IPLL) based on a stator flux observer is introduced for position estimation.Compared to the conventional phase-locked loop scheme,the IPLL offers a more robust disturbance rejection capability and thus reduces the flux model errors at lower speeds.Experimental results substantiate the feasibility of the extended low-speed operation using the model-based sensorless control approach.
文摘We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics collimator（AFOC）,and the PL control is realized by the phase modulator（PM）.Cascaded and simultaneous controls of TT and PL using stochastic parallel gradient descent（SPGD） algorithm are investigated in this paper.Two-fiber-laser-,four-fiber-laser-,and six-fiber-laser-arrays are employed to study the TT and PL control.In the cascaded control system,only one high-speed CMOS camera is used to collect beam data and a computer is used as the controller.In a simultaneous control system one high-speed CMOS camera and one photonic detector（PD） are employed,and a computer and a control circuit based on field programmable gate array（FPGA） are used as the controllers.Experimental results reveal that both cascaded and simultaneous controls of TT using AFOC and PL using PM in fiber laser array are feasible and effective.Cascaded control is more effective in static control situation and simultaneous control can be applied to the dynamic control system directly.The control signals of simultaneous PL and TT disturb each other obviously and TT and PL control may compete with each other,so the control effect is limited.
基金The National Natural Science Foundation of China(No. 60974116 )the Research Fund of Aeronautics Science (No.20090869007)Specialized Research Fund for the Doctoral Program of Higher Education (No. 200902861063)
文摘In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.
基金This work has been partly supported by National Natural Science Foundation of China(NSFC 51877093,51707079,and 51807075),National Key Research and Development Program of China(Project ID:YS2018YFGH000200),and Fund。
文摘In this paper,a sensorless control strategy of a permanent magnet synchronous machine(PMSM)based on an improved rotor flux observer(IFO)is proposed.Due to the unknown integral initial value and the high harmonics caused by current sampling and inverter nonlinearities,the flux linkage estimated by traditional rotor flux observer may be inaccurate.In order to address these issues,a self-adaptive band-pass filter(SABPF)is designed to eliminate the DC component and high-frequency harmonics of the estimated equivalent rotor flux linkage.Furthermore,in order to avoid that the design of PI parameter is influenced by the amplitude of equivalent rotor flux linkage,an improved phase-locked loop(IPLL)is employed to obtain the rotor speed and to normalize the estimated equivalent rotor flux linkage.In addition,angle shift caused by an SABPF is compensated to improve the accuracy of the estimated flux linkage angle.Besides,the parameter robustness of this method is analyzed in detail.Finally,simulation and experimental results demonstrate the effectiveness and parameter robustness of the proposed method.
文摘In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is controlled by a 16-bit single chip microprocessor.A new type of frequency and phase detector is presented in detail,An adaptive method isadopted in speed controller.A three mode control scheme is used.These techniques are very use-ful to the improvement of the dynamic behavior of digital AC motor drive system.Experimental results show that the system is of good stability,high precision and good dynam-ic performance.
文摘A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z2A7)the Scienceand Technology Program of Zhejiang Province (No.2008C16017)
文摘A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.
基金Funded by the Communication System Project of Jiangsu Provincial Education Committee under grant No.JHB04010
文摘A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.
基金supported by the National Key R&D Program of China(No.2022YFB2402800).
文摘Most permanent magnet synchronous generator(PMSG)based wind generation systems currently employ grid-following control,relying on a phase-locked loop(PLL)for grid connection.However,it leads to a lack of inertia support in the system.To address this,the virtual inertia control(VIC)is crucial for improvement,yet it introduces potential instability due to torsional oscillation interaction with PLL and low-frequency oscillations,which is an underexplored area.This paper presents a comprehensive analysis of the grid-connected PMSG-based wind generation system.It confirms the necessity of employing a full-order model for studying stability on the quasi-electromechanical timescale(QET)by a comparison with the reduced-order model.Then,a comprehensive modal analysis is conducted to analyze the effect of VIC parameters,shaft inertia time constant,PLL parameters,and torsional oscillation damping(TOD)controller gain on the interaction of QET oscillations under two typical control strategies.The occurrence of interaction and mode conversion is observed when the oscillation frequency and root loci of the torsional,PLL,and low-frequency oscillations are close.Finally,a theoretical analysis is validated via simulation verification in Simulink.These findings offer a valuable guidance for industrial PMSG applications considering VIC.
基金This work was supported by the National Natural Science Foundation of China(51877159,51637007,U1866601).
文摘When the power grid suffers from grid faults that cause phase disturbances,the grid-connected converter becomes destabilized by the interaction between the phase-locked loop(PLL)and the control loop.In this paper,the stability of the PLL affected by the control loop under transient grid faults is studied.First,the equivalent model of the PLL under the influence of the control loop is established.Then,different response processes of PLLs under the ground fault with various control parameters are qualitatively analyzed.Furthermore,a small-signal model is proposed to assess the stability of the PLL under different control loop parameters.The system poles can be calculated to show the physical origin of the instability.Finally,simulations of a three-phase 21-level modular multilevel converter(MMC)built in PSCAD and a down-scale experiment is performed to verify the parameter influence of the control loop on the PLL.
基金supported by the National Key R&D Program of China(No.2020YFB0408302)Strategic Priority Research Program of Chinese Academy of Sciences(No.XDB43030400)+1 种基金National Natural Science Foundation of China(No.91938302)Key Project of Chinese Academy of Sciences(No.ZDRWKT-2019-1-01-0302)。
文摘An optical phase locking method based on direct phase control is proposed.The core of this method is to synchronize the carrier by directly changing the phase of the local beam.The corresponding experimental device and the supporting algorithm were configured to verify the feasibility of this method.Phase locking can be completed without cycle skipping,and the acquisition time is 530 ns.Without an optical preamplifier,a sensitivity of-34.4 d Bm is obtained,and the bit error rate is 10^(-9) for 2.5 Gbit/s binary phase-shift keying modulation.The measured standard deviation of the phase error is 5.2805°.
文摘A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.
基金supported by the National Key Research and Development Program of China(2017YFB0902901)and National Natural Science Foundation of China(51627811).
文摘Increasing penetration of power electronic(PE)grid-tied devices has caused more and more dynamic problems with unknown mechanisms.Since grid operation asks for a certain voltage amplitude and frequency level when there is a power imbalance,roles of the PE grid-tied devices during dynamics must be characterized as internal voltage response under power excitation,in which the voltage vector evolves through its timevarying amplitude and frequency.Existing modeling works,unfortunately,fail to recognize amplitude and frequency modulation essence of grid voltage during dynamics,so corresponding linear models are inapplicable to small-perturbation grid dynamic analysis.Thus,taking current control timescale of grid-tied voltage source converter(VSC)for example,this paper establishes a model with active and reactive current excitation and internal voltage amplitude and frequency response.Especially,the role of the terminal voltage detection-based phase-locked loop(PLL)in the excitation-response relationship is revealed.Linearization is conducted by clarifying amplitude and frequency operating points and corresponding increments of AC signals.This model intuitively reflects the evolution of internal voltage amplitude and frequency excited by active and reactive currents,which represents characteristics of the device during dynamics.Then,simulations for verification of the linear model and time-varying nature of amplitude and frequency are presented.Features of the characteristics of VSC are preliminarily discussed.
基金supported by the National Natural Science Foundation for Distinguished Young Scholars of China under Grant 52225704.
文摘This study examines whether power systems using 100%phase-locked loop(PLL)-synchronized voltage-source converters(VSCs)can operate independently.While grid-forming(GFM)technology lacks a unified definition,independent operation remains its core requirement.Current views incorrectly associate PLL synchronization solely with grid-following(GFL)control,assuming that PLL-based equipment requires support from synchronous generators or GFM devices.We challenge this by revealing three essential conditions for independent operation in fully PLL-synchronized systems:stable device synchronization,controllable node voltages,and adjustable system frequency.Through detailed analysis and tests,we prove these requirements can be met in 100%VSC systems using PLL synchronization.This discovery breaks the traditional link between operational independence and synchronization methods.Our findings offer new insights for developing renewable-dominated grids.The above three conditions have been proven to be achievable in a 100%PLL-synchronized VSC system.
基金supported by National Natural Science Foundation of China(No.51877061).
文摘The negative-sequence voltage is often caused by the asymmetrical fault in the AC system,as well as the harmonics after the symmetrical fault at the AC side of inverter in line commutated converter based high-voltage DC(LCC-HVDC).The negative-sequence voltage affects the phase-locked loop(PLL)and the inverter control,thus the inverter is vulnerable to the subsequent commutation failure(SCF).In this paper,the analytical expression of the negative-sequence voltage resulting from the symmetrical fault with the commutation voltage is derived using the switching function and Fourier decomposition.The analytical expressions of the outputs of the PLL and inverter control with respect to time are derived to quantify the contribution of the negative-sequence voltage to the SCF.To deal with the AC component of the input signals in the PLL and the inverter control due to the negative-sequence voltage,the existing proportional-integral controls of the PLL,constant current control,and constant extinction angle control are replaced by the linear active disturbance rejection control against the SCF.Simulation results verify the contributing factors to the SCF.The proposed control reduces the risk of SCF and improves the recovery speed of the system under different fault conditions.
基金supported by the National Natural Science Foundation of China(No.U2066602)。
文摘This letter studies large-disturbance stability of the power system with a synchronous generator(SG)and a converter-interfaced generation(CIG)connected to infinite bus.The power system is multi-timescale and first simplified.It is shown that the boundary of region of attraction(ROA)of the simplified model is composed of stable manifolds of unstable equilibrium point(UEP)or semi-singular point(SSP),named anchor points,and singular surface pieces.The type of anchor point determines the dominant instability pattern of the power system.When the anchor point is UEP or SSP,the dominant instability pattern is the instability of rotor angle of SG or the instability of phase-locked loop and outer control loop(OCL)of CIG,respectively.Transition of dominant instability pattern can be analyzed with the relative position relationship between UEP and SSP.The effect of OCL is discussed.When the OCL is activated,the ROA becomes smaller and the system is more prone to instability of CIG.It is necessary to consider the OCL when studying the large-disturbance stability of the power system.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.
文摘A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector（PFD）,and a new feedback structure is utilized in the charge pump（CP） for ultra-low voltage applications.The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power.In addition,several novel design techniques,such as removing the tail current source,are demonstrated to cut down the phase noise.Implemented in the SMIC 0.13μm RF CMOS process and operated at 0.8 V supply voltage,the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz.The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply.The occupied chip area of the PFD and CP is 100×100μm^2.The chip occupies 0.63 mm^2,and draws less than 6.54 mW from a 0.8 V supply.
