In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communicat...In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.展开更多
A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the...A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.展开更多
随着高清电视和网络媒体的快速发展,音视频同步技术在广播电视节目制作中的重要性日益突出。通过对当前音视频同步系统的分析,深入研究节目时钟参考(Program Clock Reference,PCR)、显示时间戳(Presentation Time Stamp,PTS)/解码时间戳...随着高清电视和网络媒体的快速发展,音视频同步技术在广播电视节目制作中的重要性日益突出。通过对当前音视频同步系统的分析,深入研究节目时钟参考(Program Clock Reference,PCR)、显示时间戳(Presentation Time Stamp,PTS)/解码时间戳(Decoding Time Stamp,DTS)、音视频缓冲区控制等关键技术在实际制作环境中的应用。基于自适应缓冲区控制的音视频同步方案能将音视频延迟控制在±15 ms以内,满足广播级节目制作要求。展开更多
This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is cal...This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 um CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the onchip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv-step, excluding the reference＇s power consumption.展开更多
This paper presents an 11-bit 200MS/s subrange S AR ADC with an integrated reference buffer in 65nm CMOS.The proposed ADC employs a 3.5-bit flash ADC for coarse conversion,and a compact timing scheme at the flash/SAR ...This paper presents an 11-bit 200MS/s subrange S AR ADC with an integrated reference buffer in 65nm CMOS.The proposed ADC employs a 3.5-bit flash ADC for coarse conversion,and a compact timing scheme at the flash/SAR boundary to speed up the conversion.The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation.Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation.In addition,the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3dB at 200MS/s.It consumes 3.91mW from a 1.2V supply,including the reference buffer.展开更多
基金Supported by the National High Technology Research and Development Program of China(No.2009AA01Z105)the Ministry of EducationIntel Special Foundation for Information Technology(No.MOE-INTEL-08-05)the Postdoctoral Science Foundation of China(No.20080440942,200902432)
文摘In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011607)the State Key Laboratory of China
文摘A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.
文摘随着高清电视和网络媒体的快速发展,音视频同步技术在广播电视节目制作中的重要性日益突出。通过对当前音视频同步系统的分析,深入研究节目时钟参考(Program Clock Reference,PCR)、显示时间戳(Presentation Time Stamp,PTS)/解码时间戳(Decoding Time Stamp,DTS)、音视频缓冲区控制等关键技术在实际制作环境中的应用。基于自适应缓冲区控制的音视频同步方案能将音视频延迟控制在±15 ms以内,满足广播级节目制作要求。
基金Supported by National Natural Science Foundation of China（60434030,60673178,and 60472076） and National Basic Research Program of China（973 Program）（2007CB307106）
基金Project supported by the Major National Science & Technology Program of China(No.2010ZX03001-004-02)
文摘This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 um CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the onchip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv-step, excluding the reference＇s power consumption.
基金supported by the Zhongxing Telecommunication Equipment CorporationBeijing Microelectronics Technology Institute
文摘This paper presents an 11-bit 200MS/s subrange S AR ADC with an integrated reference buffer in 65nm CMOS.The proposed ADC employs a 3.5-bit flash ADC for coarse conversion,and a compact timing scheme at the flash/SAR boundary to speed up the conversion.The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation.Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation.In addition,the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3dB at 200MS/s.It consumes 3.91mW from a 1.2V supply,including the reference buffer.
