The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation met...The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.展开更多
The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locati...The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.展开更多
In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design...In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.展开更多
A solution is imperatively expected to meet the efficient contention resolution schemes for managing simultaneous access requests to the communication resources on the Network on Chip (NoC). Based on the ideas of conf...A solution is imperatively expected to meet the efficient contention resolution schemes for managing simultaneous access requests to the communication resources on the Network on Chip (NoC). Based on the ideas of conflict-free transmission, priority-based service, and dynamic self-adaptation to loading, this paper presents a novel scheduling algorithm for Medium Access Control (MAC) in NoC with the researches of the communication structure features of 2D mesh. The algorithm gives priority to guarantee the Quality of Service (QoS) for local input port as well as dynamic adjustment of the performance of the other ports along with input load change. The theoretical model of this algorithm is established with Markov chain and probability generating function. Mathematical analysis is made on the mean queue length and the mean inquiry cyclic time of the system. Simulated experiments are conducted to test the accuracy of the model. It turns out that the findings from theoretical analysis correspond well with those from simulated experiments. Further more, the analytical findings of the system performance demonstrate that the algorithm enables effectively strengthen the fairness and stability of data transmissions in NoC.展开更多
Aiming at the applications of NOC(network on chip)technology in rising scale and complexity on chip systems,a Torus structure and corresponding route algorithm for NOC is proposed.This Torus structure improves traditi...Aiming at the applications of NOC(network on chip)technology in rising scale and complexity on chip systems,a Torus structure and corresponding route algorithm for NOC is proposed.This Torus structure improves traditional Torus topology and redefines the denotations of the routers.Through redefining the router denotations and changing the original router locations,the Torus structure for NOC application is reconstructed.On the basis of this structure,a dead-lock and live-lock free route algorithm is designed according to dimension increase.System C is used to implement this structure and the route algorithm is simulated.In the four different traffic patterns,average,hotspot 13%,hotspot 67%and transpose,the average delay and normalization throughput of this Torus structure are evaluated.Then,the performance of delay and throughput between this Torus and Mesh structure is compared.The results indicate that this Torus structure is more suitable for NOC applications.展开更多
Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic partic...Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.展开更多
Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In th...Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.展开更多
The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning...The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.展开更多
Mapping of three-dimensional network on chip is a key problem in the research of three-dimensional network on chip. The quality of the mapping algorithm used di- rectly affects the communication efficiency between IP ...Mapping of three-dimensional network on chip is a key problem in the research of three-dimensional network on chip. The quality of the mapping algorithm used di- rectly affects the communication efficiency between IP cores and plays an important role in the optimization of power consumption and throughput of the whole chip. In this paper, ba- sic concepts and related work of three-dimensional network on chip are introduced. Quantum-behaved particle swarm op- timization algorithm is applied to the mapping problem of three-dimensional network on chip for the first time. Sim- ulation results show that the mapping algorithm based on quantum-behaved particle swarm algorithm has faster con- vergence speed with much better optimization performance compared with the mapping algorithm based on particle swarm algorithm. It also can effectively reduce the power consumption of mapping of three-dimensional network on chip.展开更多
For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation...For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper.The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock.Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register,and then control the wrapper to sample input/output data.Sender wrapper and receiver wrapper consist of C elements and threshold gates,which ensure the quasi delay-insensitive characteristics and enhance the robustness.Simulations under different technology corners are implemented based on SMIC 0.18μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW.Its advantages of high-throughput,low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.展开更多
The conventional microwell-based platform for construction of organoid models exhibits limitations in precision oncology applications because of low-speed growth and high variability. Here, we established organoid mod...The conventional microwell-based platform for construction of organoid models exhibits limitations in precision oncology applications because of low-speed growth and high variability. Here, we established organoid models on a nested array chip for fast and reproducible drug testing using 50% matrigel. First, we constructed mouse small intestinal and colonic organoid models. Compared with the conventional microwell-based platform, the mouse organoids on the chip showed accelerated growth and improved reproducibility due to the nested design of the chip. The design of the chip provides miniaturized and uniform shaping of the matrigel that allows the organoid to grow in a concentrated and controlled manner. Next, a patient-derived organoid(PDO) model from colorectal cancer tissues was successfully generated and characterized on the chip. Finally, the PDO models on the chip, from three patients, were implemented for high-throughput drug screening using nine treatment regimens. The drug sensitivity testing on the PDO models showed good quality control with a coefficient of variation under 10% and a Z’ factor of more than 0.7. More importantly, the drug responses on the chip recapitulate the heterogeneous response of individual patients, as well as showing a potential correlation with clinical outcomes. Therefore,the organoid model coupled with the nested array chip platform provides a fast and reproducible means for predicting drug responses to accelerate precise oncology.展开更多
Network on chip(NoC)is an infrastructure providing a communication platform to multiprocessor chips.Furthermore,the wormhole-switching method,which shares resources,was used to increase its efficiency;however,this can...Network on chip(NoC)is an infrastructure providing a communication platform to multiprocessor chips.Furthermore,the wormhole-switching method,which shares resources,was used to increase its efficiency;however,this can lead to congestion.Moreover,dealing with this congestion consumes more energy and correspondingly leads to increase in power consumption.Furthermore,consuming more power results in more heat and increases thermal fluctuations that lessen the life span of the infrastructures and,more importantly,the network’s performance.Given these complications,providing a method that controls congestion is a significant design challenge.In this paper,a fuzzy logic congestion control routing algorithm is presented to enhance the NoC’s performance when facing congestion.To avoid congestion,the proposed algorithm employs the occupied input buffer and the total occupied buffers of the neighboring nodes along with the maximum possible path diversity with minimal path length from instant neighbors to the destination as the selection parameters.To enhance the path selection function,the uncertainty of the fuzzy logic algorithm is used.As a result,the average delay,power consumption,and maximum delay are reduced by 14.88%,7.98%,and 19.39%,respectively.Additionally,the proposed method enhances the throughput and the total number of packets received by 14.9%and 11.59%,respectively.To show the significance,the proposed algorithm is examined using transpose traffic patterns,and the average delay is improved by 15.3%.The average delay is reduced by 3.8%in TMPEG-4(treble MPEG-4),36.6%in QPIP(quadruplicate PIP),and 20.9%in TVOPD(treble VOPD).展开更多
As the number of cores in chip multiprocessors （CMPs） increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocess...As the number of cores in chip multiprocessors （CMPs） increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocessors still faces three hurdles： design complexity, performance and scalability. This paper proposes Cache Coherent Network on Chip （CCNoC）, a scheme that decouples cache coherency maintenance from processors and shared L2 caches and implements it completely in network on chip to free up processors and shared L2 caches from the chore of maintaining coherency, thereby reduces design complexity of CMPs. In this way, CCNoC also improves the performance of cache coherence protocol through reducing directory access latency and enhances scalability by avoiding massive directories overhead in shared L2 caches. In CCNoC, coherence state caches and active directory caches are implemented in the network interface components of network on chip to maintain cache coherence states for blocks in L1 caches and manage directory information for recently accessed blocks in L2 caches respectively. CCNoC provides a scalable CMP framework to tackle cache coherency which is the foundation of CMP. This paper evaluates the performance of CCNoC. Experimental results show that for a 16-core system, CCNoC improves performance by 3% on average over the conventional chip multiprocessor and by 10% at best, while reduces storage overhead by 1.8% and saves directory storage by 88%, showing good scalability.展开更多
Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter....Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.展开更多
Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mes...Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.展开更多
We characterize the current crowding effect for microwave radiation on a chip surface based on a quantum wide-field microscope combining a wide-field reconstruction technique. A swept microwave signal with the power o...We characterize the current crowding effect for microwave radiation on a chip surface based on a quantum wide-field microscope combining a wide-field reconstruction technique. A swept microwave signal with the power of 0–30 d Bm is supplied to a dumbbell-shaped microstrip antenna, and the significant differences in microwave magnetic-field amplitudes attributed to the current crowding effect are experimentally observed in a 2.20 mm ×1.22 mm imaging area. The normalized microwave magnetic-field amplitude along the horizontal geometrical center of the image area further demonstrates the feasibility of the characterization of the current crowding effect. The experiments indicate the proposal can be qualified for the characterization of the anomalous area of the radio-frequency chip surface.展开更多
With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to sol...With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.展开更多
The single event effects(SEEs)evaluations caused by atmospheric neutrons were conducted on three different convolutional neural network(CNN)models(Yolov3,MNIST,and ResNet50)in the atmospheric neutron irradiation spect...The single event effects(SEEs)evaluations caused by atmospheric neutrons were conducted on three different convolutional neural network(CNN)models(Yolov3,MNIST,and ResNet50)in the atmospheric neutron irradiation spectrometer(ANIS)at the China Spallation Neutron Source(CSNS).The Yolov3 and MNIST models were implemented on the XILINX28-nm system-on-chip(So C).Meanwhile,the Yolov3 and ResNet50 models were deployed on the XILINX 16-nm Fin FET Ultra Scale+MPSoC.The atmospheric neutron SEEs on the tested CNN systems were comprehensively evaluated from six aspects,including chip type,network architecture,deployment methods,inference time,datasets,and the position of the anchor boxes.The various types of SEE soft errors,SEE cross-sections,and their distribution were analyzed to explore the radiation sensitivities and rules of 28-nm and 16-nm SoC.The current research can provide the technology support of radiation-resistant design of CNN system for developing and applying high-reliability,long-lifespan domestic artificial intelligence chips.展开更多
基金Supported by the Natural Science Foundation of China(61076019)the China Postdoctoral Science Foundation(20100481134)+1 种基金the Natural Science Foundation of Jiangsu Province(BK2008387)the Graduate Student Innovation Foundation of Jiangsu Province(CX07B-105z)~~
文摘The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.
基金This work was supported by the National Natural Science Foundation of China(Nos.11575138,11835006,11690040,11690043,and 11705216)the Innovation Center of Radiation Application(No.KFZC2019050321)the China Scholarships Council program(No.201906280343).
文摘The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.
基金Project supported by the IC Special Foundation of Shanghai Municipal Commission of Science and Technology (Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information (Grant No.090344)the Shanghai High-Tech Industrialization of New Energy Vehicles (Grant No.09625029),and the Graduate Innovation Foundation of Shanghai University
文摘In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.
基金Supported by the National Natural Science Foundation of China(No.61072079)
文摘A solution is imperatively expected to meet the efficient contention resolution schemes for managing simultaneous access requests to the communication resources on the Network on Chip (NoC). Based on the ideas of conflict-free transmission, priority-based service, and dynamic self-adaptation to loading, this paper presents a novel scheduling algorithm for Medium Access Control (MAC) in NoC with the researches of the communication structure features of 2D mesh. The algorithm gives priority to guarantee the Quality of Service (QoS) for local input port as well as dynamic adjustment of the performance of the other ports along with input load change. The theoretical model of this algorithm is established with Markov chain and probability generating function. Mathematical analysis is made on the mean queue length and the mean inquiry cyclic time of the system. Simulated experiments are conducted to test the accuracy of the model. It turns out that the findings from theoretical analysis correspond well with those from simulated experiments. Further more, the analytical findings of the system performance demonstrate that the algorithm enables effectively strengthen the fairness and stability of data transmissions in NoC.
基金the National Natural Science Fundation of China(60575031).
文摘Aiming at the applications of NOC(network on chip)technology in rising scale and complexity on chip systems,a Torus structure and corresponding route algorithm for NOC is proposed.This Torus structure improves traditional Torus topology and redefines the denotations of the routers.Through redefining the router denotations and changing the original router locations,the Torus structure for NOC application is reconstructed.On the basis of this structure,a dead-lock and live-lock free route algorithm is designed according to dimension increase.System C is used to implement this structure and the route algorithm is simulated.In the four different traffic patterns,average,hotspot 13%,hotspot 67%and transpose,the average delay and normalization throughput of this Torus structure are evaluated.Then,the performance of delay and throughput between this Torus and Mesh structure is compared.The results indicate that this Torus structure is more suitable for NOC applications.
基金Project supported by the National Natural Science Foundation of China(Grant No.12305303)the Natural Science Foundation of Hunan Province of China(Grant Nos.2023JJ40520,2021JJ40444,and 2019JJ30019)+3 种基金the Research Foundation of Education Bureau of Hunan Province of China(Grant No.20A430)the Science and Technology Innovation Program of Hunan Province(Grant No.2020RC3054)the Natural Science Basic Research Plan in the Shaanxi Province of China(Grant No.2023-JC-QN-0015)the Doctoral Research Fund of University of South China。
文摘Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.
文摘Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.
文摘The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.
文摘Mapping of three-dimensional network on chip is a key problem in the research of three-dimensional network on chip. The quality of the mapping algorithm used di- rectly affects the communication efficiency between IP cores and plays an important role in the optimization of power consumption and throughput of the whole chip. In this paper, ba- sic concepts and related work of three-dimensional network on chip are introduced. Quantum-behaved particle swarm op- timization algorithm is applied to the mapping problem of three-dimensional network on chip for the first time. Sim- ulation results show that the mapping algorithm based on quantum-behaved particle swarm algorithm has faster con- vergence speed with much better optimization performance compared with the mapping algorithm based on particle swarm algorithm. It also can effectively reduce the power consumption of mapping of three-dimensional network on chip.
基金Supported by the National Natural Science Foundation of China under Grant Nos.60725415,60971066the National High-Tech Research and Development 863 Program of China under Grant Nos.2009AA01Z258,2009AA01Z260the National Science & Technology Important Project under Grant No.2009ZX01034-002-001-005.
文摘For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper.The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock.Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register,and then control the wrapper to sample input/output data.Sender wrapper and receiver wrapper consist of C elements and threshold gates,which ensure the quasi delay-insensitive characteristics and enhance the robustness.Simulations under different technology corners are implemented based on SMIC 0.18μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW.Its advantages of high-throughput,low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.
基金supported by grants from the National Natural Science Foundation of China (No.82174086)the Beijing Natural Science Foundation (No.7222273)+3 种基金the Beijing Xisike Clinical Oncology Research Foundation (Nos.Y-xsk2021-0004 and Y-XD202001-0172)the Youth Talents Promotion Project of China Association of Chinese Medicine (No.2020-QNRC2-08)the Clinical Medicine Plus X-Young Scholars Project of Peking University (No.BMU2021MX009)the Peking University People’s Hospital Research and Development Funds (No.RDY2020-18)。
文摘The conventional microwell-based platform for construction of organoid models exhibits limitations in precision oncology applications because of low-speed growth and high variability. Here, we established organoid models on a nested array chip for fast and reproducible drug testing using 50% matrigel. First, we constructed mouse small intestinal and colonic organoid models. Compared with the conventional microwell-based platform, the mouse organoids on the chip showed accelerated growth and improved reproducibility due to the nested design of the chip. The design of the chip provides miniaturized and uniform shaping of the matrigel that allows the organoid to grow in a concentrated and controlled manner. Next, a patient-derived organoid(PDO) model from colorectal cancer tissues was successfully generated and characterized on the chip. Finally, the PDO models on the chip, from three patients, were implemented for high-throughput drug screening using nine treatment regimens. The drug sensitivity testing on the PDO models showed good quality control with a coefficient of variation under 10% and a Z’ factor of more than 0.7. More importantly, the drug responses on the chip recapitulate the heterogeneous response of individual patients, as well as showing a potential correlation with clinical outcomes. Therefore,the organoid model coupled with the nested array chip platform provides a fast and reproducible means for predicting drug responses to accelerate precise oncology.
文摘Network on chip(NoC)is an infrastructure providing a communication platform to multiprocessor chips.Furthermore,the wormhole-switching method,which shares resources,was used to increase its efficiency;however,this can lead to congestion.Moreover,dealing with this congestion consumes more energy and correspondingly leads to increase in power consumption.Furthermore,consuming more power results in more heat and increases thermal fluctuations that lessen the life span of the infrastructures and,more importantly,the network’s performance.Given these complications,providing a method that controls congestion is a significant design challenge.In this paper,a fuzzy logic congestion control routing algorithm is presented to enhance the NoC’s performance when facing congestion.To avoid congestion,the proposed algorithm employs the occupied input buffer and the total occupied buffers of the neighboring nodes along with the maximum possible path diversity with minimal path length from instant neighbors to the destination as the selection parameters.To enhance the path selection function,the uncertainty of the fuzzy logic algorithm is used.As a result,the average delay,power consumption,and maximum delay are reduced by 14.88%,7.98%,and 19.39%,respectively.Additionally,the proposed method enhances the throughput and the total number of packets received by 14.9%and 11.59%,respectively.To show the significance,the proposed algorithm is examined using transpose traffic patterns,and the average delay is improved by 15.3%.The average delay is reduced by 3.8%in TMPEG-4(treble MPEG-4),36.6%in QPIP(quadruplicate PIP),and 20.9%in TVOPD(treble VOPD).
基金supported by the National Natural Science Foundation of China under Grant Nos.60970002,60833004,60773146, and 60673145.
文摘As the number of cores in chip multiprocessors （CMPs） increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocessors still faces three hurdles： design complexity, performance and scalability. This paper proposes Cache Coherent Network on Chip （CCNoC）, a scheme that decouples cache coherency maintenance from processors and shared L2 caches and implements it completely in network on chip to free up processors and shared L2 caches from the chore of maintaining coherency, thereby reduces design complexity of CMPs. In this way, CCNoC also improves the performance of cache coherence protocol through reducing directory access latency and enhances scalability by avoiding massive directories overhead in shared L2 caches. In CCNoC, coherence state caches and active directory caches are implemented in the network interface components of network on chip to maintain cache coherence states for blocks in L1 caches and manage directory information for recently accessed blocks in L2 caches respectively. CCNoC provides a scalable CMP framework to tackle cache coherency which is the foundation of CMP. This paper evaluates the performance of CCNoC. Experimental results show that for a 16-core system, CCNoC improves performance by 3% on average over the conventional chip multiprocessor and by 10% at best, while reduces storage overhead by 1.8% and saves directory storage by 88%, showing good scalability.
文摘Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.
基金supported by the National Natural Science Foundation of China under Grant No.60425413
文摘Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.
基金supported by the National Natural Science Foundation of China (Nos.51821003,52275551,and 51922009)Shanxi Scholarship Council of China (No.2021–117)。
文摘We characterize the current crowding effect for microwave radiation on a chip surface based on a quantum wide-field microscope combining a wide-field reconstruction technique. A swept microwave signal with the power of 0–30 d Bm is supplied to a dumbbell-shaped microstrip antenna, and the significant differences in microwave magnetic-field amplitudes attributed to the current crowding effect are experimentally observed in a 2.20 mm ×1.22 mm imaging area. The normalized microwave magnetic-field amplitude along the horizontal geometrical center of the image area further demonstrates the feasibility of the characterization of the current crowding effect. The experiments indicate the proposal can be qualified for the characterization of the anomalous area of the radio-frequency chip surface.
文摘With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.
基金Project supported by the National Natural Science Foundation of China(Grant No.12305303)the Natural Science Foundation of Hunan Province of China(Grant Nos.2023JJ40520,2024JJ2044,and 2021JJ40444)+3 种基金the Science and Technology Innovation Program of Hunan Province,China(Grant No.2020RC3054)the Postgraduate Scientific Research Innovation Project of Hunan Province,China(Grant No.CX20240831)the Natural Science Basic Research Plan in the Shaanxi Province of China(Grant No.2023-JC-QN0015)the Doctoral Research Fund of University of South China(Grant No.200XQD033)。
文摘The single event effects(SEEs)evaluations caused by atmospheric neutrons were conducted on three different convolutional neural network(CNN)models(Yolov3,MNIST,and ResNet50)in the atmospheric neutron irradiation spectrometer(ANIS)at the China Spallation Neutron Source(CSNS).The Yolov3 and MNIST models were implemented on the XILINX28-nm system-on-chip(So C).Meanwhile,the Yolov3 and ResNet50 models were deployed on the XILINX 16-nm Fin FET Ultra Scale+MPSoC.The atmospheric neutron SEEs on the tested CNN systems were comprehensively evaluated from six aspects,including chip type,network architecture,deployment methods,inference time,datasets,and the position of the anchor boxes.The various types of SEE soft errors,SEE cross-sections,and their distribution were analyzed to explore the radiation sensitivities and rules of 28-nm and 16-nm SoC.The current research can provide the technology support of radiation-resistant design of CNN system for developing and applying high-reliability,long-lifespan domestic artificial intelligence chips.
