This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventiona...Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventional optical phase-locked loops is limited,and link delays restrict the control bandwidth,which makes it a challenge to achieve a continuously reliable optical link.This paper presents an event-timing-based phase detection method that overcomes the monotonic phase discrimination range limitation of conventional phase-locked loops through dual-edge timestamp recording,achieving an optical phase measurement resolution on the order of 10 attoseconds.With such a technique,we established a 7-segment-cascaded optical link over 1402km of commercial fiber while sharing dense wavelength division multiplexing(DWDM)channels with live telecom traffic.The system maintained continuous operation for 11.7 days without phase cycle slips despite encountering 15 km aerial fiber noise up to 21000 rad^(2)·Hz^(−1)·km^(−1)at 1 Hz.Relative instabilities of the link are 3.7×10^(−15)at 1 s and 3.9×10^(−20)at 100000 s.展开更多
A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the cente...A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.展开更多
Indoor positioning with high accuracy plays an important role in different application scenar-ios.As a widely used mobile communication signal,the Long-Term Evolution(LTE)network can be well received in indoor and out...Indoor positioning with high accuracy plays an important role in different application scenar-ios.As a widely used mobile communication signal,the Long-Term Evolution(LTE)network can be well received in indoor and outdoor environments.This article studies a method of using different reference signals in the LTE downlink for carrier phase time of arrival(TOA)estimation.Specifically,a solution is proposed and a multipath tracking Software Defined Receiver(SDR)is developed for indoor positioning.With our SDR indoor positioning system,the pilot signals of the LTE signals are firstly obtained by the coarse synchronization and demodulation.Then,with the assistance of the pilot signals,the time delay acquisition,the multipath estimating delay lock loop(MEDLL)algorithm,and the multipath anomaly detection are sequentially carried out to obtain navigation observations of received signals.Furthermore,to compare the perfor-mance of different pilot signals,the Secondary Synchronous Signals(SSS)and Cell Reference Signals(CRS)are used as pilot signals for carrier phase-based TOA estimation,respectively.Finally,to quantify the accuracy of our multipath tracking SDR,indoor field tests are carried out in a conference environment,where an LTE base station is installed for commercial use.Our test results based on CRS show that,in the static test scenarios,the TOA accuracy measured by the 1-σerror interval is about 0.5 m,while in the mobile environment,the probability of range accuracy within 1.0 m is 95%.展开更多
Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the proble...Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.展开更多
A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low pow...A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.展开更多
This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input dat...This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.展开更多
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
基金supported by the National Key Research and Development Program of China(Grant No.2020YFC2200103)the Shandong Provincial Natural Science Foundation(Grant Nos.ZR2022LLZ006 and ZR2022LLZ011)+1 种基金the Innovation Program for Quantum Science and Technology(Grant Nos.2021ZD0300904 and 2021ZD0300903)the Key R&D Plan of Shandong Province(Grant No.2023CXPT105)。
文摘Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventional optical phase-locked loops is limited,and link delays restrict the control bandwidth,which makes it a challenge to achieve a continuously reliable optical link.This paper presents an event-timing-based phase detection method that overcomes the monotonic phase discrimination range limitation of conventional phase-locked loops through dual-edge timestamp recording,achieving an optical phase measurement resolution on the order of 10 attoseconds.With such a technique,we established a 7-segment-cascaded optical link over 1402km of commercial fiber while sharing dense wavelength division multiplexing(DWDM)channels with live telecom traffic.The system maintained continuous operation for 11.7 days without phase cycle slips despite encountering 15 km aerial fiber noise up to 21000 rad^(2)·Hz^(−1)·km^(−1)at 1 Hz.Relative instabilities of the link are 3.7×10^(−15)at 1 s and 3.9×10^(−20)at 100000 s.
文摘A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.
基金supported by The National Natural Science Foundation of China[grant number 42171417]the Special Fund of Hubei Luojia Laboratory[grant number 220100008]the Key Research and Development Program of Hubei Province[grant number 2021BAA166].
文摘Indoor positioning with high accuracy plays an important role in different application scenar-ios.As a widely used mobile communication signal,the Long-Term Evolution(LTE)network can be well received in indoor and outdoor environments.This article studies a method of using different reference signals in the LTE downlink for carrier phase time of arrival(TOA)estimation.Specifically,a solution is proposed and a multipath tracking Software Defined Receiver(SDR)is developed for indoor positioning.With our SDR indoor positioning system,the pilot signals of the LTE signals are firstly obtained by the coarse synchronization and demodulation.Then,with the assistance of the pilot signals,the time delay acquisition,the multipath estimating delay lock loop(MEDLL)algorithm,and the multipath anomaly detection are sequentially carried out to obtain navigation observations of received signals.Furthermore,to compare the perfor-mance of different pilot signals,the Secondary Synchronous Signals(SSS)and Cell Reference Signals(CRS)are used as pilot signals for carrier phase-based TOA estimation,respectively.Finally,to quantify the accuracy of our multipath tracking SDR,indoor field tests are carried out in a conference environment,where an LTE base station is installed for commercial use.Our test results based on CRS show that,in the static test scenarios,the TOA accuracy measured by the 1-σerror interval is about 0.5 m,while in the mobile environment,the probability of range accuracy within 1.0 m is 95%.
基金National Key Research and Development Program of China(No.2018YFE0208200)National Natural Science Foundation of China(Nos.61971307,61905175,51775377)+5 种基金National Key Research and Development Plan Project(No.2020YFB2010800)The Fok Ying Tung Education Foundation(No.171055)China Postdoctoral Science Foundation(No.2020M680878)Guangdong Province Key Research and Development Plan Project(No.2020B0404030001)Tianjin Science and Technology Plan Project(No.20YDTPJC01660)Project of Foreign Affairs Committee of China Aviation Development Sichuan Gas Turbine Research Institute(Nos.GJCZ-2020-0040,GJCZ-2020-0041)。
文摘Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.
基金supported by the National Science Foundation of China(No.61106027)the 333 Talent Project of Jiangsu Province,China(No. BRA2011115)
文摘A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.
文摘This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.
