In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are de...In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are derived by permuting the matrices of the corresponding RC-LDPC block codes,are systematic and have maximum encoding memory.Simulation results show that the proposed RC-LDPC convolutional codes with belief propagation(BP) decoding collectively offer a steady improvement on performance compared with the block counterparts over the binary-input additive white Gaussian noise channels(BI-AWGNCs).展开更多
Low-density parity-check （LDPC） codes were first presented by Gallager in 1962. They are linear block codes and their bit error rate （BER） performance approaches remarkably close to the Shannon limit. The LDPC cod...Low-density parity-check （LDPC） codes were first presented by Gallager in 1962. They are linear block codes and their bit error rate （BER） performance approaches remarkably close to the Shannon limit. The LDPC codes created much interest after the rediscovery by Mackay and Neal in 1995. This paper introduces some new LDPC codes by considering some combinatorial structures. We present regular LDPC codes based on group divisible designs which have Tanner graphs free of four-cycles.展开更多
A low-complexity algorithm is proposed in this paper in order to optimize irregular low-density parity-check （LDPC） codes.The algorithm proposed can calculate the noise threshold by means of a one-dimensional densit...A low-complexity algorithm is proposed in this paper in order to optimize irregular low-density parity-check （LDPC） codes.The algorithm proposed can calculate the noise threshold by means of a one-dimensional density evolution and search the optimal degree profiles with fast-convergence differential evolution,so that it has a lower complexity and a faster convergence speed.Simulation resuits show that the irregular LDPC codes optimized by the presented algorithm can also perform better than Turbo codes at moderate block length even with less computation cost.展开更多
The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space ...The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.展开更多
In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The...In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The receiver performs two iterative decoding loops. In the outer loop, the soft information is exchanged between the PDA detector and the LDPC decoder. In the inner loop, it is exchanged between variable node and check node decoders inside the LDPC decoder. On the light of the Extrinsic Information Transfer (EXIT) chart technique, an LDPC code degree profile optimization algorithm is developed for the doubly-iterative receiver. Simulation results show the doubly-receiver with optimized irregular LDPC code can have a better performance than the one with the regular one.展开更多
In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the ...In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the analysis of the code rate and parameters of these eight kinds of structures, we find that the construction of low-density parity-check matrix tends to be more flexible and the parameter variability is enhanced. We propose that the current development cost should be lower with the progress of electronic technology and we need research on more practical Low-Density Parity-Check Codes (LDPC). Combined with the application of the quantum distribution key, we urgently need to explore the research direction of relevant theories and technologies of LDPC codes in other fields of quantum information in the future.展开更多
A great challenge faced by wireless sensor networks(WSNs) is to reduce energy consumption of sensor nodes. Fortunately, the data gathering via random sensing can save energy of sensor nodes. Nevertheless, its randomne...A great challenge faced by wireless sensor networks(WSNs) is to reduce energy consumption of sensor nodes. Fortunately, the data gathering via random sensing can save energy of sensor nodes. Nevertheless, its randomness and density usually result in difficult implementations, high computation complexity and large storage spaces in practical settings. So the deterministic sparse sensing matrices are desired in some situations. However,it is difficult to guarantee the performance of deterministic sensing matrix by the acknowledged metrics. In this paper, we construct a class of deterministic sparse sensing matrices with statistical versions of restricted isometry property(St RIP) via regular low density parity check(RLDPC) matrices. The key idea of our construction is to achieve small mutual coherence of the matrices by confining the column weights of RLDPC matrices such that St RIP is satisfied. Besides, we prove that the constructed sensing matrices have the same scale of measurement numbers as the dense measurements. We also propose a data gathering method based on RLDPC matrix. Experimental results verify that the constructed sensing matrices have better reconstruction performance, compared to the Gaussian, Bernoulli, and CSLDPC matrices. And we also verify that the data gathering via RLDPC matrix can reduce energy consumption of WSNs.展开更多
QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easil...QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on ＂half-change＂ Gray coding are researched. Because of the probable error impact of QLC NAND cell＇s voltage change, the solution of generating the soft information after XOR（exclusive OR） the soft bits by internal read mechanism is presented for Low-Density Parity-Check（LDPC） Belief Propagation（BP） decoding in QLC design for its system level application.展开更多
Aiming at the problem that quasi-cyclic low density parity check(QC-LDPC) codes may have the error floor in the high signal to noise ratio(SNR) region, a new construction method of the QC-LDPC codes with the low error...Aiming at the problem that quasi-cyclic low density parity check(QC-LDPC) codes may have the error floor in the high signal to noise ratio(SNR) region, a new construction method of the QC-LDPC codes with the low error floor is proposed. The basic matrix of the method is based on the progressive edge growth(PEG) algorithm and the improved eliminate elementary trapping sets(EETS) algorithm so as to eliminate the elementary trapping sets in the basic matrix,then the Zig-Zag method is used to construct the cyclic shift matrix which is used to extend the basic matrix in order to construct the parity check matrix. The method not only can improve the error floor in the high SNR region, but also can flexibly design the code length and code rate. The simulation results show that at the bit error rate of 10-6, the PEG-trapping-Zig-Zag(PTZZ)-QC-LDPC(3024,1512) codes with the code rate of 0.5, compared with the PEG-Zig-Zag(PZZ)-QC-LDPC(3024,1512) codes and the PEG-QC-LDPC(3024,1512) codes, can respectively improve the net coding gain of 0.1 dB and 0.16 dB. The difference among the bit error rate performance curves will become better with the increase of the SNR. In addition, the PTZZ-QC-LDPC(3024,1512) codes have no error floor above the SNR of 2.2 dB.展开更多
As the 2nd generation digital terrestrial television broadcasting(DTTB)standard,digital terrestrial/television multimedia broadcasting-advanced(DTMB-A)can provide higher spectrum efficiency and transmission reliabilit...As the 2nd generation digital terrestrial television broadcasting(DTTB)standard,digital terrestrial/television multimedia broadcasting-advanced(DTMB-A)can provide higher spectrum efficiency and transmission reliability by adopting flexible frame structure and advanced forward error correction coding compared with the 1 st generation DTTB systems.In order to increase the flexibility and robustness of the DTTB network,the frequency reuse scheme of factor one(reuse-1)is proposed,where the same RF channel is used by different stations covering the adjacent service areas.However,it demands a very low carrier-tonoise ratio(C/N)threshold below 0 dB at the DTTB physical layer.In this paper,a robust broadcasting technique is proposed based on DTMB-A with newly designed low-rate low density parity check(LDPC)codes.By adopting quasi-cyclic(QC)Raptor-like structure and progressive lifting method,the high performance low-rate LDPC codes are designed supporting multiple code lengths.Both density-evolution analyses and laboratory measurements demonstrate that DTMB-A with low-rate coding can complete the demodulation reliably with the C/N threshold below0 d B,which is one important necessary condition to support frequency reuse-1 scheme.展开更多
This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great me...This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.展开更多
Three families of low-density parity-check （LDPC） codes are constructed based on the totally isotropic subspaces of symplectic, unitary, and orthogonal spaces over finite fields, respectively. The minimum distances ...Three families of low-density parity-check （LDPC） codes are constructed based on the totally isotropic subspaces of symplectic, unitary, and orthogonal spaces over finite fields, respectively. The minimum distances of the three families of LDPC codes in some special cases are settled.展开更多
Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is de...Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verily the approach is tully integrated in a four-metal double-poly 0.35 lam complementary metal oxide semiconductor （CMOS） technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable lbr space- and power-constrained spacecraft system.展开更多
基金the National Natural Science Foundation of China(Nos.61401164,61471131 and 61201145)the Natural Science Foundation of Guangdong Province(No.2014A030310308)
文摘In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are derived by permuting the matrices of the corresponding RC-LDPC block codes,are systematic and have maximum encoding memory.Simulation results show that the proposed RC-LDPC convolutional codes with belief propagation(BP) decoding collectively offer a steady improvement on performance compared with the block counterparts over the binary-input additive white Gaussian noise channels(BI-AWGNCs).
基金Supported by the National Natural Science Foundation of China(Grant Nos.1107105611201114)
文摘Low-density parity-check （LDPC） codes were first presented by Gallager in 1962. They are linear block codes and their bit error rate （BER） performance approaches remarkably close to the Shannon limit. The LDPC codes created much interest after the rediscovery by Mackay and Neal in 1995. This paper introduces some new LDPC codes by considering some combinatorial structures. We present regular LDPC codes based on group divisible designs which have Tanner graphs free of four-cycles.
基金Leading Academic Discipline Project of Shanghai Municipal Education Commission,China(No.J51801)Shanghai Second Polytechnic University Foundation,China(No.QD209008)Leading Academic Discipline Project of Shanghai Second Polytechnic University,China(No.XXKZD1302)
文摘A low-complexity algorithm is proposed in this paper in order to optimize irregular low-density parity-check （LDPC） codes.The algorithm proposed can calculate the noise threshold by means of a one-dimensional density evolution and search the optimal degree profiles with fast-convergence differential evolution,so that it has a lower complexity and a faster convergence speed.Simulation resuits show that the irregular LDPC codes optimized by the presented algorithm can also perform better than Turbo codes at moderate block length even with less computation cost.
基金Supported by the National Natural Science Foundation of China (61205116)
文摘The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.
基金Supported by the National Natural Science Foundation of China (No. 60772061)Science Foundation of Nanjing University of Posts and Telecommunications (No. NY207132)
文摘In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The receiver performs two iterative decoding loops. In the outer loop, the soft information is exchanged between the PDA detector and the LDPC decoder. In the inner loop, it is exchanged between variable node and check node decoders inside the LDPC decoder. On the light of the Extrinsic Information Transfer (EXIT) chart technique, an LDPC code degree profile optimization algorithm is developed for the doubly-iterative receiver. Simulation results show the doubly-receiver with optimized irregular LDPC code can have a better performance than the one with the regular one.
文摘In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the analysis of the code rate and parameters of these eight kinds of structures, we find that the construction of low-density parity-check matrix tends to be more flexible and the parameter variability is enhanced. We propose that the current development cost should be lower with the progress of electronic technology and we need research on more practical Low-Density Parity-Check Codes (LDPC). Combined with the application of the quantum distribution key, we urgently need to explore the research direction of relevant theories and technologies of LDPC codes in other fields of quantum information in the future.
基金supported by the National Natural Science Foundation of China(61307121)ABRP of Datong(2017127)the Ph.D.’s Initiated Research Projects of Datong University(2013-B-17,2015-B-05)
文摘A great challenge faced by wireless sensor networks(WSNs) is to reduce energy consumption of sensor nodes. Fortunately, the data gathering via random sensing can save energy of sensor nodes. Nevertheless, its randomness and density usually result in difficult implementations, high computation complexity and large storage spaces in practical settings. So the deterministic sparse sensing matrices are desired in some situations. However,it is difficult to guarantee the performance of deterministic sensing matrix by the acknowledged metrics. In this paper, we construct a class of deterministic sparse sensing matrices with statistical versions of restricted isometry property(St RIP) via regular low density parity check(RLDPC) matrices. The key idea of our construction is to achieve small mutual coherence of the matrices by confining the column weights of RLDPC matrices such that St RIP is satisfied. Besides, we prove that the constructed sensing matrices have the same scale of measurement numbers as the dense measurements. We also propose a data gathering method based on RLDPC matrix. Experimental results verify that the constructed sensing matrices have better reconstruction performance, compared to the Gaussian, Bernoulli, and CSLDPC matrices. And we also verify that the data gathering via RLDPC matrix can reduce energy consumption of WSNs.
文摘QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on ＂half-change＂ Gray coding are researched. Because of the probable error impact of QLC NAND cell＇s voltage change, the solution of generating the soft information after XOR（exclusive OR） the soft bits by internal read mechanism is presented for Low-Density Parity-Check（LDPC） Belief Propagation（BP） decoding in QLC design for its system level application.
基金financially supported by the National Natural Science Foundation of China(No.61471075)the Program for Postgraduate Science Research and Innovation of Chongqing University of Posts and Telecommunications(Chongqing Municipal Education Commission)(No.CYS17241)the Undergraduate Science Research Training Project for Chongqing University of Posts and Telecommunication(No.201901013)
文摘Aiming at the problem that quasi-cyclic low density parity check(QC-LDPC) codes may have the error floor in the high signal to noise ratio(SNR) region, a new construction method of the QC-LDPC codes with the low error floor is proposed. The basic matrix of the method is based on the progressive edge growth(PEG) algorithm and the improved eliminate elementary trapping sets(EETS) algorithm so as to eliminate the elementary trapping sets in the basic matrix,then the Zig-Zag method is used to construct the cyclic shift matrix which is used to extend the basic matrix in order to construct the parity check matrix. The method not only can improve the error floor in the high SNR region, but also can flexibly design the code length and code rate. The simulation results show that at the bit error rate of 10-6, the PEG-trapping-Zig-Zag(PTZZ)-QC-LDPC(3024,1512) codes with the code rate of 0.5, compared with the PEG-Zig-Zag(PZZ)-QC-LDPC(3024,1512) codes and the PEG-QC-LDPC(3024,1512) codes, can respectively improve the net coding gain of 0.1 dB and 0.16 dB. The difference among the bit error rate performance curves will become better with the increase of the SNR. In addition, the PTZZ-QC-LDPC(3024,1512) codes have no error floor above the SNR of 2.2 dB.
基金supported in part by the National Natural Science Foundation of China(NSFC)under Grant 61931015the Peng Cheng Laboratory under Grant PCL2021A10+1 种基金the Science,Technology and Innovation Commission of Shenzhen Municipality(No.JSGG20201103095805015)sponsored by Tsinghua University-Yunnan Mobile Digital TV Company Ltd.,Joint Research Center(JCICBN)。
文摘As the 2nd generation digital terrestrial television broadcasting(DTTB)standard,digital terrestrial/television multimedia broadcasting-advanced(DTMB-A)can provide higher spectrum efficiency and transmission reliability by adopting flexible frame structure and advanced forward error correction coding compared with the 1 st generation DTTB systems.In order to increase the flexibility and robustness of the DTTB network,the frequency reuse scheme of factor one(reuse-1)is proposed,where the same RF channel is used by different stations covering the adjacent service areas.However,it demands a very low carrier-tonoise ratio(C/N)threshold below 0 dB at the DTTB physical layer.In this paper,a robust broadcasting technique is proposed based on DTMB-A with newly designed low-rate low density parity check(LDPC)codes.By adopting quasi-cyclic(QC)Raptor-like structure and progressive lifting method,the high performance low-rate LDPC codes are designed supporting multiple code lengths.Both density-evolution analyses and laboratory measurements demonstrate that DTMB-A with low-rate coding can complete the demodulation reliably with the C/N threshold below0 d B,which is one important necessary condition to support frequency reuse-1 scheme.
基金Science and Technology on Avionics Integration Laboratory and Aeronautical Science Foundation of China (20115551022)
文摘This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.
基金This work was supported in part by the National Natural Science Foundation of China （Grant Nos. 11271004, 11371121, 11471096）.
文摘Three families of low-density parity-check （LDPC） codes are constructed based on the totally isotropic subspaces of symplectic, unitary, and orthogonal spaces over finite fields, respectively. The minimum distances of the three families of LDPC codes in some special cases are settled.
文摘Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verily the approach is tully integrated in a four-metal double-poly 0.35 lam complementary metal oxide semiconductor （CMOS） technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable lbr space- and power-constrained spacecraft system.
