The paper studies a cycle storage system with fixed capacity to monitor fuze battery＇s working voltage and noise,solving the problems of small capacity and low sample frequency.A 4 MB cycle sampling space is designed...The paper studies a cycle storage system with fixed capacity to monitor fuze battery＇s working voltage and noise,solving the problems of small capacity and low sample frequency.A 4 MB cycle sampling space is designed by adopting the negative delay technology,which implements the function of recording 4 MB data before triggered and then sequentially recording 50 MB data to ensure that the host computer recovers the voltage and noise data correctly and effectively.Two pieces of Flash work alternately to avoid the time conflict between commands programming and data writing.This method can make efficient use of storage space,recording the information before triggered,therefore it ensures the reliability and validity of the measured data.展开更多
The paper is concerned with the generalization of synthetic theory to the modeling of phenomena such as the Bauschinger negative effect, creep delay, reverse and inverse creep. Detailed calculations of plastic/creep s...The paper is concerned with the generalization of synthetic theory to the modeling of phenomena such as the Bauschinger negative effect, creep delay, reverse and inverse creep. Detailed calculations of plastic/creep strains are accompanied with the construction of loading surfaces that enhance the understanding of the processes studied. The calculated results show satisfactory agreement with experiments.展开更多
A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applie...A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.展开更多
文摘The paper studies a cycle storage system with fixed capacity to monitor fuze battery＇s working voltage and noise,solving the problems of small capacity and low sample frequency.A 4 MB cycle sampling space is designed by adopting the negative delay technology,which implements the function of recording 4 MB data before triggered and then sequentially recording 50 MB data to ensure that the host computer recovers the voltage and noise data correctly and effectively.Two pieces of Flash work alternately to avoid the time conflict between commands programming and data writing.This method can make efficient use of storage space,recording the information before triggered,therefore it ensures the reliability and validity of the measured data.
文摘The paper is concerned with the generalization of synthetic theory to the modeling of phenomena such as the Bauschinger negative effect, creep delay, reverse and inverse creep. Detailed calculations of plastic/creep strains are accompanied with the construction of loading surfaces that enhance the understanding of the processes studied. The calculated results show satisfactory agreement with experiments.
文摘A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.
