This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended ...This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.展开更多
We study the problem of multiple node upset （MNU） using three-dimensional device simulation. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We compare the MNU ...We study the problem of multiple node upset （MNU） using three-dimensional device simulation. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We compare the MNU with multiple bit upset （MBU）,and find that their characteristics are different. Methods to avoid MNU are also discussed.展开更多
The microstructure and hardness of a 2024 aluminum alloy subjected tomulti-pass upsetting extrusion at ambient temperature were studied. Experimental results indicatedthat with the number of upsetting extrusion passes...The microstructure and hardness of a 2024 aluminum alloy subjected tomulti-pass upsetting extrusion at ambient temperature were studied. Experimental results indicatedthat with the number of upsetting extrusion passes increasing, the grains of the alloy are graduallyrefined and the hardness increases correspondingly. After ten passes of upsetting extrusionprocessing, the grain size decreases to less than 200 nm in diameter and the sample maintains itsoriginal shape, while the hardness is double owing to equal-axial ultrafine grains and workhardening effect caused by large plastic deformation.展开更多
In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up （SEL） sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset （MCU） is the para...In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up （SEL） sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset （MCU） is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM＇s MCU sensitivity. After the neutron experiment, we test the devices＇ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices＇ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge （ESD） testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.展开更多
For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide th...For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.展开更多
In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 ...In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.展开更多
基金Sponsored by the Opening Project of National Key Laboratory of Science and Technology on Reliability PhysicsApplication Technology of Electrical Component(Grant No.ZHD200903)
文摘This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.
文摘We study the problem of multiple node upset （MNU） using three-dimensional device simulation. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We compare the MNU with multiple bit upset （MBU）,and find that their characteristics are different. Methods to avoid MNU are also discussed.
基金This project is financially supported by the Natural Science Foundation (No. E5305293) of South China University of Technology.
文摘The microstructure and hardness of a 2024 aluminum alloy subjected tomulti-pass upsetting extrusion at ambient temperature were studied. Experimental results indicatedthat with the number of upsetting extrusion passes increasing, the grains of the alloy are graduallyrefined and the hardness increases correspondingly. After ten passes of upsetting extrusionprocessing, the grain size decreases to less than 200 nm in diameter and the sample maintains itsoriginal shape, while the hardness is double owing to equal-axial ultrafine grains and workhardening effect caused by large plastic deformation.
文摘In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up （SEL） sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset （MCU） is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM＇s MCU sensitivity. After the neutron experiment, we test the devices＇ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices＇ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge （ESD） testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.
基金supported by the National Natural Science Foundation of China(Nos.12035019 and 11690041).
文摘For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.
基金supported by the National Natural Science Foundation of China(Grant No.61504169)the Preliminary Research Program of National University of Defense Technology of China(Grant No.0100066314001)
文摘In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.
