The paper intfoduces a PC-DSP based real-time digital simulator which is portable in size and aimed at the closed-loop testing of various types of protective relays for their design and application. The simulator can ...The paper intfoduces a PC-DSP based real-time digital simulator which is portable in size and aimed at the closed-loop testing of various types of protective relays for their design and application. The simulator can be widely used in not only concerning utilities but also manufacturers and research / certification institutes because of its many functions. The hardware architecture and software implementation of the simulator are described. The main features and functions of the simulator are also展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
In the storage ring RF system of Shanghai Synchrotron Radiation Facility,the clock distribution and the local oscillator are two parts of the digital low level radio frequency hardware board.In this paper,we designed ...In the storage ring RF system of Shanghai Synchrotron Radiation Facility,the clock distribution and the local oscillator are two parts of the digital low level radio frequency hardware board.In this paper,we designed and produced the clock distribution and the local oscillator board using the AD9858 and AD9510 chips.The results show that the phase noise of the local oscillator signal is lower than 100dBc/Hz with 50 kHz offset.展开更多
Digital media offer unique opportunities for museums to bring to life the secrets and stories of their historical collections.To bring insight into the process of developing digital media exhibits,this paper presents ...Digital media offer unique opportunities for museums to bring to life the secrets and stories of their historical collections.To bring insight into the process of developing digital media exhibits,this paper presents the perspective of a creative practitioner in approaching technology-and media-based interpretation for collection objects.It follows the Time,Culture and Identity digital workshop held in Beijing in October 2019,which explored and shared ideas about collaborative research and interdisciplinary practice in digital interpretation between academics,institutions,creative practitioners,and developers.Following the direction of the workshop,the paper takes as its focus the clocks and automatons of the imperial collection at the Palace Museum in Beijing.Observations are based on the author’s practice-led experience in running a design studio,Harmonic Kinetic,developing new media exhibits using digital technology and audiovisual media for museums,galleries,and exhibitions in the UK,including the Science Museum,V&A,Barbican,Tate,and the Tower of London.Taking a broad interaction-design-led outlook,the paper explores a personal design perspective for developing interpretive content and considers the particular opportunities and approaches these historical devices suggest.The paper concludes with a final section that reviews the process and reflects on outcomes from the Time,Culture and Identity digital workshop.This explored possibilities for an interpretive exhibit on the Country Scene clock from the Palace Museum collection.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledg...With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gatin...A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.展开更多
Multi-functional dendrometer is a kind of forestry tool that can measure multiple factors of forest.By combining sensor technology and computer technology,a digital multi-function dendrometer has been developed,which ...Multi-functional dendrometer is a kind of forestry tool that can measure multiple factors of forest.By combining sensor technology and computer technology,a digital multi-function dendrometer has been developed,which integrated the functions of measuring height,distance,azimuth, slope,elevation,form quotient of any parts of the stem into one body at the same test.The dendrometer can fit the complex forest environment,solve the difficult problems in aspects of plant height,measure distance,central diameter and form quotient of breast height.The accuracy can meet the requirements of general forest survey.展开更多
文摘The paper intfoduces a PC-DSP based real-time digital simulator which is portable in size and aimed at the closed-loop testing of various types of protective relays for their design and application. The simulator can be widely used in not only concerning utilities but also manufacturers and research / certification institutes because of its many functions. The hardware architecture and software implementation of the simulator are described. The main features and functions of the simulator are also
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
基金Supported by Shanghai Synchrotron Radiation Facility
文摘In the storage ring RF system of Shanghai Synchrotron Radiation Facility,the clock distribution and the local oscillator are two parts of the digital low level radio frequency hardware board.In this paper,we designed and produced the clock distribution and the local oscillator board using the AD9858 and AD9510 chips.The results show that the phase noise of the local oscillator signal is lower than 100dBc/Hz with 50 kHz offset.
文摘Digital media offer unique opportunities for museums to bring to life the secrets and stories of their historical collections.To bring insight into the process of developing digital media exhibits,this paper presents the perspective of a creative practitioner in approaching technology-and media-based interpretation for collection objects.It follows the Time,Culture and Identity digital workshop held in Beijing in October 2019,which explored and shared ideas about collaborative research and interdisciplinary practice in digital interpretation between academics,institutions,creative practitioners,and developers.Following the direction of the workshop,the paper takes as its focus the clocks and automatons of the imperial collection at the Palace Museum in Beijing.Observations are based on the author’s practice-led experience in running a design studio,Harmonic Kinetic,developing new media exhibits using digital technology and audiovisual media for museums,galleries,and exhibitions in the UK,including the Science Museum,V&A,Barbican,Tate,and the Tower of London.Taking a broad interaction-design-led outlook,the paper explores a personal design perspective for developing interpretive content and considers the particular opportunities and approaches these historical devices suggest.The paper concludes with a final section that reviews the process and reflects on outcomes from the Time,Culture and Identity digital workshop.This explored possibilities for an interpretive exhibit on the Country Scene clock from the Palace Museum collection.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
文摘With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
基金The Research Project of China Military Department (No6130325)
文摘A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.
文摘Multi-functional dendrometer is a kind of forestry tool that can measure multiple factors of forest.By combining sensor technology and computer technology,a digital multi-function dendrometer has been developed,which integrated the functions of measuring height,distance,azimuth, slope,elevation,form quotient of any parts of the stem into one body at the same test.The dendrometer can fit the complex forest environment,solve the difficult problems in aspects of plant height,measure distance,central diameter and form quotient of breast height.The accuracy can meet the requirements of general forest survey.
