通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信...通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信号理论设计文字运算电路;然后采用文字0、文字1和文字2非运算电路实现三值SRAM的功能,利用传输门控制反馈回路降低三值写操作的动态功耗;最后实验验证,所设计的电路逻辑功能正确且与传统交叉耦合SRAM相比写速度提高49.2%。展开更多
通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)和多值存储原理的研究,提出一种基于CNFET的单端口三值SRAM设计方案。该方案首先利用碳纳米管的多阈值特性设计三值反相器,并采用交叉耦合方式实现三值数据的...通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)和多值存储原理的研究,提出一种基于CNFET的单端口三值SRAM设计方案。该方案首先利用碳纳米管的多阈值特性设计三值反相器,并采用交叉耦合方式实现三值数据的存储;其次结合读写共用的单端口方法,减少互连线数量;然后采用隔离和切断交叉耦合技术,增强三值数据存储的稳定性;最后通过HSPICE仿真,结果表明所设计的电路逻辑功能正确,且与传统CMOS设计的三值SRAM相比读写速度提高24%。展开更多
Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% o...Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.展开更多
Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NM...Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.展开更多
文摘通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信号理论设计文字运算电路;然后采用文字0、文字1和文字2非运算电路实现三值SRAM的功能,利用传输门控制反馈回路降低三值写操作的动态功耗;最后实验验证,所设计的电路逻辑功能正确且与传统交叉耦合SRAM相比写速度提高49.2%。
文摘通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)和多值存储原理的研究,提出一种基于CNFET的单端口三值SRAM设计方案。该方案首先利用碳纳米管的多阈值特性设计三值反相器,并采用交叉耦合方式实现三值数据的存储;其次结合读写共用的单端口方法,减少互连线数量;然后采用隔离和切断交叉耦合技术,增强三值数据存储的稳定性;最后通过HSPICE仿真,结果表明所设计的电路逻辑功能正确,且与传统CMOS设计的三值SRAM相比读写速度提高24%。
文摘Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.
基金Project supported by the National Natural Science Foundation of China(No.61076032)the Key Project of Zhejiang Provincial Natural Science of China(No.Z1111219)the K.C.Wong Magna Fund in Ningbo University,China
文摘Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.
