Voltage scaling has been extensively used in industry for decades to reduce power consumption.In recent years,exploring digital circuit operation in moderate inversion has created an interest among researchers due to ...Voltage scaling has been extensively used in industry for decades to reduce power consumption.In recent years,exploring digital circuit operation in moderate inversion has created an interest among researchers due to its immense capability to provide a perfect tradeoff between high performance and low energy operation.But circuits operating in moderate inversion are susceptible to process variations and variability.To compute variability,statistical parameters such as the probability density function(PDF)and cumulative distribution function(CDF)are required.This paper presents an analytical model framework for delay calculations utilizing log skew normal distribution for ultradeep submicron technology nodes up to 22 nm.The CDF of the proposed model is utilized to calculate minimum and maximum delays with 3σ-accuracy providing better accuracy than the conventional methods.The obtained results are also compared with Monte Carlo simulations with errors lying within the acceptable range of 2%-4%.展开更多
This paper presents an integrated complementary metal oxide semiconductor （CMOS） low power low noise amplifier （LNA） for global positioning system （GPS） receivers. To achieve low power dissipation, the MOS trans...This paper presents an integrated complementary metal oxide semiconductor （CMOS） low power low noise amplifier （LNA） for global positioning system （GPS） receivers. To achieve low power dissipation, the MOS transistors in the proposed LNA are biased in moderate inversion region. It is implemented by SMIC 180 nm 1P6M CMOS process. The experiment results show that a gain of 12.14 dB@l.57 GHz is achieved with low noise figure （NF） of 1.62 dB. The power consumption of the circuit is 1.5 mW at supply voltage of 1.8 V. The ratio of gain to dc power consumption is 8 dB/mW. The size of the LNA is only 980 μm ×720 μm including the pads.展开更多
文摘Voltage scaling has been extensively used in industry for decades to reduce power consumption.In recent years,exploring digital circuit operation in moderate inversion has created an interest among researchers due to its immense capability to provide a perfect tradeoff between high performance and low energy operation.But circuits operating in moderate inversion are susceptible to process variations and variability.To compute variability,statistical parameters such as the probability density function(PDF)and cumulative distribution function(CDF)are required.This paper presents an analytical model framework for delay calculations utilizing log skew normal distribution for ultradeep submicron technology nodes up to 22 nm.The CDF of the proposed model is utilized to calculate minimum and maximum delays with 3σ-accuracy providing better accuracy than the conventional methods.The obtained results are also compared with Monte Carlo simulations with errors lying within the acceptable range of 2%-4%.
基金supported by the Beijing Leading Subject Foundation Project (XK100070525)
文摘This paper presents an integrated complementary metal oxide semiconductor （CMOS） low power low noise amplifier （LNA） for global positioning system （GPS） receivers. To achieve low power dissipation, the MOS transistors in the proposed LNA are biased in moderate inversion region. It is implemented by SMIC 180 nm 1P6M CMOS process. The experiment results show that a gain of 12.14 dB@l.57 GHz is achieved with low noise figure （NF） of 1.62 dB. The power consumption of the circuit is 1.5 mW at supply voltage of 1.8 V. The ratio of gain to dc power consumption is 8 dB/mW. The size of the LNA is only 980 μm ×720 μm including the pads.
