This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed...This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper.展开更多
The paper introduces a temperature control systembased on AT89C51 single-chip-microprocessor, and discussesthe principle , hardware structure, and software design of thissystem in detail.
There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable...There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.展开更多
The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation met...The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.展开更多
针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动...针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动声呐实时信号处理算法的加速方案。首先研究适合边缘端部署的声呐信号处理算法;然后设计基于MPSoC的加速计算结构,将数字下变频、逆/快速傅里叶变换、波束形成等具有高计算复杂性的处理步骤移植到可编程逻辑端,实现显著加速;最后将目标检测等复杂度较低的步骤部署在处理器系统端,实现更高的灵活性。仿真及湖上试验结果表明,提出的方案可在数据更新周期的41%时间内完成1帧回波数据的实时处理,并可在复杂水下环境下实时有效探测运动目标。该方案在水下UUV主动声呐探测领域具有广阔的应用前景。展开更多
为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理...为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。展开更多
It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to sim...It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.展开更多
A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC...A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
文摘This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper.
文摘The paper introduces a temperature control systembased on AT89C51 single-chip-microprocessor, and discussesthe principle , hardware structure, and software design of thissystem in detail.
基金Supported by the Guangzhou Key Technology R&D Program (No.2007Z2-D0011)
文摘There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.
基金Supported by the Natural Science Foundation of China(61076019)the China Postdoctoral Science Foundation(20100481134)+1 种基金the Natural Science Foundation of Jiangsu Province(BK2008387)the Graduate Student Innovation Foundation of Jiangsu Province(CX07B-105z)~~
文摘The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.
文摘针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动声呐实时信号处理算法的加速方案。首先研究适合边缘端部署的声呐信号处理算法;然后设计基于MPSoC的加速计算结构,将数字下变频、逆/快速傅里叶变换、波束形成等具有高计算复杂性的处理步骤移植到可编程逻辑端,实现显著加速;最后将目标检测等复杂度较低的步骤部署在处理器系统端,实现更高的灵活性。仿真及湖上试验结果表明,提出的方案可在数据更新周期的41%时间内完成1帧回波数据的实时处理,并可在复杂水下环境下实时有效探测运动目标。该方案在水下UUV主动声呐探测领域具有广阔的应用前景。
文摘为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。
基金Supported by the National Natural Science Foundation of China for Distinguished Young Scholar under Grant No. 60325205 the National High Technology Development 863 Program of China under Grants No. 2002AA110010, No. 2005AA110010 No. 2005AA119020, and the National Grand Fundamental Research 973 Program of China under Grant No. 2005CB321600.
文摘It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.
基金Supported by the Ministerial Level Advanced Research Foundation (SP240012)
文摘A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
