Simulators are generally used during the design of computer architectures. Typically, different simulators with different levels of complexity, speed and accuracy are used. However, for early design space exploration,...Simulators are generally used during the design of computer architectures. Typically, different simulators with different levels of complexity, speed and accuracy are used. However, for early design space exploration, simulators with less complexity, high simulation speed and reasonable accuracy are desired. It is also required that these simulators have a short development time and that changes in the design require less effort in the implementation in order to perform experiments and see the effects of changes in the design. These simulators are termed high-level simulators in the context of computer architecture. In this paper, we present multiple levels of abstractions in a high-level simulation of a general-purpose many-core system, where the objective of every level is to improve the accuracy in simulation without significantly affecting the complexity and simulation speed.展开更多
Based on the three-dimensional particle-in-cell （PIC） method and Compute Unified Device Architecture （CUDA）, a parallel particle simulation code combined with a graphic processor unit （GPU） has been developed fo...Based on the three-dimensional particle-in-cell （PIC） method and Compute Unified Device Architecture （CUDA）, a parallel particle simulation code combined with a graphic processor unit （GPU） has been developed for the simulation of charge-exchange （CEX） xenon ions in the plume of an ion thruster. Using the proposed technique, the potential and CEX plasma distribution are calculated for the ion thruster plume surrounding the DS1 spacecraft at different thrust levels. The simulation results are in good agreement with measured CEX ion parameters reported in literature, and the CPU＇s results are equal to a CPU＇s. Compared with a single CPU Intel Core 2 E6300, 16-processor GPU NVIDIA GeForce 9400 GT indicates a speedup factor of 3.6 when the total macro particle number is 1.1 × 10^6. The simulation results also reveal how the back flow CEX plasma affects the spacecraft floating potential, which indicates that the plume of the ion thruster is indeed able to alleviate the extreme negative floating potentials of spacecraft in geosynchronous orbit.展开更多
The design of a pixel processor of a real-time CIG (Computer Image Generation) system is summarized. The system has been brought into use. In order to adopt ASIC (Application-Specific integrated Circuit) technology in...The design of a pixel processor of a real-time CIG (Computer Image Generation) system is summarized. The system has been brought into use. In order to adopt ASIC (Application-Specific integrated Circuit) technology in the design of the new system, the VHDL (Very high speed integrated circuit Hardware Description Language) is used and a re-design and simulation strategy is planed.展开更多
Simulation is an important and useful technique helping users understand and model real life systems. Once built, the models can run proving realistic results. This supports making decisions on a more logical and scie...Simulation is an important and useful technique helping users understand and model real life systems. Once built, the models can run proving realistic results. This supports making decisions on a more logical and scientific basis. The paper introduces method of simulation, and describes various types of its application. The authors used the method of analysis of the creation and implementation of the programme code. The authors compared parallel instruction of computing defined to pipelined instructions. The power of simulation is that a common model can be used to design a large variety of systems. An important aspect of the simulation method is that a simulation model is designed to be repeated in actual computer systems, especially in multicore processors. For this reason, it is important to minimize average waiting time for fetch and decode stage instructions. The objective of the research is to prove that the parallel operation of programme code is faster than sequential operation code on the multi processor architecture. The system modeling uses methods and simulation on the parallel computer systems is very precise. The time benefit gained in simulation of mathematical model on the pipeline processor is higher than the one in simulation of mathematical model on the multi processors computer system.展开更多
The evolutions of the electron temperatures of Muminum plasmas produced with 0.351 μm laser are simulated by means of one-dimensional hydrodynamic code. The simulations show that the plasma geometry has strong influe...The evolutions of the electron temperatures of Muminum plasmas produced with 0.351 μm laser are simulated by means of one-dimensional hydrodynamic code. The simulations show that the plasma geometry has strong influence on the electron temperature＇s evolution while the effect of the flux limiter is not so significant. The simulations are in good agreement with the experiments only at some spatial points. A full comparison between the simulations and experiments indicates that the one-dimensional code is not accurate enough to characterize the laser-produced plasmas. A post-processor code based on the hydro code is developed to generate the streak image of the Thomson scattering spectra, which can be directly compared with the experimental data.展开更多
The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The pr...The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.展开更多
Satellite signal simulator for global navigation satellite system(GNSS)can evaluate the accuracy of capturing,tracing and positioning of GNSS receiver.It has significant use-value in the military and civil fields.The ...Satellite signal simulator for global navigation satellite system(GNSS)can evaluate the accuracy of capturing,tracing and positioning of GNSS receiver.It has significant use-value in the military and civil fields.The system adopts the overall design scheme of digital signal processor(DSP)and field-programmable gate array(FPGA).It consists of four modules:industrial control computer simulation software,mid-frequency signal generator,digital-to-analog(D/A)module and radio frequency(RF)module.In this paper,we test the dynamic performance of simulator using the dynamic scenes testing method,and the signal generated by the designed simulator is primarily validated.展开更多
Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. A...Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modem network processor before making chip. In order to achieve the tradeoff between performance and power, the processor simulator is used to design the architecture of network processor. Using Netbeneh, Commubench benchmark and processor simulator-SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance lnteI IXP 2800 Network processor eonfignration, optimized instruction fetch width and speed ,instruction issue width, instruction window size are analyzed and selected. Simulation resuits show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design.展开更多
Due to advances in semiconductor techniques, many-core processors have been widely used in high performance computing. However, many applications still cannot be carried out efficiently due to the memory wall, which h...Due to advances in semiconductor techniques, many-core processors have been widely used in high performance computing. However, many applications still cannot be carried out efficiently due to the memory wall, which has become a bottleneck in many-core processors. In this paper, we present a novel heterogeneous many-core processor architecture named deeply fused many-core （DFMC） for high performance computing systems. DFMC integrates management processing ele- ments （MPEs） and computing processing elements （CPEs）, which are heterogeneous processor cores for different application features with a unified ISA （instruction set architecture）, a unified execution model, and share-memory that supports cache coherence. The DFMC processor can alleviate the memory wall problem by combining a series of cooperative computing techniques of CPEs, such as multi-pattern data stream transfer, efficient register-level communication mechanism, and fast hardware synchronization technique. These techniques are able to improve on-chip data reuse and optimize memory access performance. This paper illustrates an implementation of a full system prototype based on FPGA with four MPEs and 256 CPEs. Our experimental results show that the effect of the cooperative computing techniques of CPEs is significant, with DGEMM （double-precision matrix multiplication） achieving an efficiency of 94%, FFT （fast Fourier transform） obtaining a performance of 207 GFLOPS and FDTD （finite-difference time-domain） obtaining a performance of 27 GFLOPS.展开更多
As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performan...As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors’ yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors’ performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.展开更多
文摘Simulators are generally used during the design of computer architectures. Typically, different simulators with different levels of complexity, speed and accuracy are used. However, for early design space exploration, simulators with less complexity, high simulation speed and reasonable accuracy are desired. It is also required that these simulators have a short development time and that changes in the design require less effort in the implementation in order to perform experiments and see the effects of changes in the design. These simulators are termed high-level simulators in the context of computer architecture. In this paper, we present multiple levels of abstractions in a high-level simulation of a general-purpose many-core system, where the objective of every level is to improve the accuracy in simulation without significantly affecting the complexity and simulation speed.
基金supported by National Natural Science Foundation of China (No. 10805004)Foundation of National Key Lab. of Science and Technology on Vacuum & Cryogenic of China (No. 9140C550404100C55)
文摘Based on the three-dimensional particle-in-cell （PIC） method and Compute Unified Device Architecture （CUDA）, a parallel particle simulation code combined with a graphic processor unit （GPU） has been developed for the simulation of charge-exchange （CEX） xenon ions in the plume of an ion thruster. Using the proposed technique, the potential and CEX plasma distribution are calculated for the ion thruster plume surrounding the DS1 spacecraft at different thrust levels. The simulation results are in good agreement with measured CEX ion parameters reported in literature, and the CPU＇s results are equal to a CPU＇s. Compared with a single CPU Intel Core 2 E6300, 16-processor GPU NVIDIA GeForce 9400 GT indicates a speedup factor of 3.6 when the total macro particle number is 1.1 × 10^6. The simulation results also reveal how the back flow CEX plasma affects the spacecraft floating potential, which indicates that the plume of the ion thruster is indeed able to alleviate the extreme negative floating potentials of spacecraft in geosynchronous orbit.
文摘The design of a pixel processor of a real-time CIG (Computer Image Generation) system is summarized. The system has been brought into use. In order to adopt ASIC (Application-Specific integrated Circuit) technology in the design of the new system, the VHDL (Very high speed integrated circuit Hardware Description Language) is used and a re-design and simulation strategy is planed.
文摘Simulation is an important and useful technique helping users understand and model real life systems. Once built, the models can run proving realistic results. This supports making decisions on a more logical and scientific basis. The paper introduces method of simulation, and describes various types of its application. The authors used the method of analysis of the creation and implementation of the programme code. The authors compared parallel instruction of computing defined to pipelined instructions. The power of simulation is that a common model can be used to design a large variety of systems. An important aspect of the simulation method is that a simulation model is designed to be repeated in actual computer systems, especially in multicore processors. For this reason, it is important to minimize average waiting time for fetch and decode stage instructions. The objective of the research is to prove that the parallel operation of programme code is faster than sequential operation code on the multi processor architecture. The system modeling uses methods and simulation on the parallel computer systems is very precise. The time benefit gained in simulation of mathematical model on the pipeline processor is higher than the one in simulation of mathematical model on the multi processors computer system.
基金supported by Natural Science Foundation of China (Nos. 10375064, 10275056, 10176028)the National High Technology Programs on Inertially Confined Fusion of China
文摘The evolutions of the electron temperatures of Muminum plasmas produced with 0.351 μm laser are simulated by means of one-dimensional hydrodynamic code. The simulations show that the plasma geometry has strong influence on the electron temperature＇s evolution while the effect of the flux limiter is not so significant. The simulations are in good agreement with the experiments only at some spatial points. A full comparison between the simulations and experiments indicates that the one-dimensional code is not accurate enough to characterize the laser-produced plasmas. A post-processor code based on the hydro code is developed to generate the streak image of the Thomson scattering spectra, which can be directly compared with the experimental data.
文摘The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.
基金Shanxi Provincial Science and Technology Research Fund(No.2012021013-6)
文摘Satellite signal simulator for global navigation satellite system(GNSS)can evaluate the accuracy of capturing,tracing and positioning of GNSS receiver.It has significant use-value in the military and civil fields.The system adopts the overall design scheme of digital signal processor(DSP)and field-programmable gate array(FPGA).It consists of four modules:industrial control computer simulation software,mid-frequency signal generator,digital-to-analog(D/A)module and radio frequency(RF)module.In this paper,we test the dynamic performance of simulator using the dynamic scenes testing method,and the signal generated by the designed simulator is primarily validated.
基金Sponsored by the National Defence Research Foundation of China(Grant No.413460303).
文摘Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modem network processor before making chip. In order to achieve the tradeoff between performance and power, the processor simulator is used to design the architecture of network processor. Using Netbeneh, Commubench benchmark and processor simulator-SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance lnteI IXP 2800 Network processor eonfignration, optimized instruction fetch width and speed ,instruction issue width, instruction window size are analyzed and selected. Simulation resuits show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design.
文摘Due to advances in semiconductor techniques, many-core processors have been widely used in high performance computing. However, many applications still cannot be carried out efficiently due to the memory wall, which has become a bottleneck in many-core processors. In this paper, we present a novel heterogeneous many-core processor architecture named deeply fused many-core （DFMC） for high performance computing systems. DFMC integrates management processing ele- ments （MPEs） and computing processing elements （CPEs）, which are heterogeneous processor cores for different application features with a unified ISA （instruction set architecture）, a unified execution model, and share-memory that supports cache coherence. The DFMC processor can alleviate the memory wall problem by combining a series of cooperative computing techniques of CPEs, such as multi-pattern data stream transfer, efficient register-level communication mechanism, and fast hardware synchronization technique. These techniques are able to improve on-chip data reuse and optimize memory access performance. This paper illustrates an implementation of a full system prototype based on FPGA with four MPEs and 256 CPEs. Our experimental results show that the effect of the cooperative computing techniques of CPEs is significant, with DGEMM （double-precision matrix multiplication） achieving an efficiency of 94%, FFT （fast Fourier transform） obtaining a performance of 207 GFLOPS and FDTD （finite-difference time-domain） obtaining a performance of 27 GFLOPS.
基金the National Natural Science Foundation of China (Nos. 60633060, 60606008, and 60576031)the National Key Basic Research and Development (973) Program of China (973)(Nos. 2005CB321604 and 2005CB321605)the fund of Chinese Academy of Sciences (No. 20074010) due to the President Scholarship
文摘As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors’ yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors’ performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.
