This study aimed at designing and assembling an improvised Logic Gates Simulator that can be utilized as an instructional device in basic digital electronics instruction at Caraga State University Cabadbaran Campus, P...This study aimed at designing and assembling an improvised Logic Gates Simulator that can be utilized as an instructional device in basic digital electronics instruction at Caraga State University Cabadbaran Campus, Philippines. This instructional device is believed to enhance the teaching-learning process and would also help address the scarcity of instructional equipment in the school and in the country. Descriptive method of research was employed to come up with the design of the simulator based on the course content of basic digital electronics subject. Acceptability of the improvised simulator based on standards set in this study was?gathered from the experts as respondents using a self-made questionnaire. The data were treated using average weighted mean utilizing parametric scales with verbal descriptions. Findings revealed that the improvised logic gates simulator is highly acceptable in terms of its cost and availability of components,?design and construction,operations, and troubleshooting features. It is concluded that the improvised logic gates simulator is at par in terms of standards on instructional devices based on the evaluation results of experts and is therefore recommended to be used in basic digital electronics instruction. The simulator is an innovative answer and an alternate solution to the scarcity of instructional materials and devices at Caraga State University Cabadbaran Campus.展开更多
Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computin...Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.展开更多
The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally ...The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.展开更多
文摘This study aimed at designing and assembling an improvised Logic Gates Simulator that can be utilized as an instructional device in basic digital electronics instruction at Caraga State University Cabadbaran Campus, Philippines. This instructional device is believed to enhance the teaching-learning process and would also help address the scarcity of instructional equipment in the school and in the country. Descriptive method of research was employed to come up with the design of the simulator based on the course content of basic digital electronics subject. Acceptability of the improvised simulator based on standards set in this study was?gathered from the experts as respondents using a self-made questionnaire. The data were treated using average weighted mean utilizing parametric scales with verbal descriptions. Findings revealed that the improvised logic gates simulator is highly acceptable in terms of its cost and availability of components,?design and construction,operations, and troubleshooting features. It is concluded that the improvised logic gates simulator is at par in terms of standards on instructional devices based on the evaluation results of experts and is therefore recommended to be used in basic digital electronics instruction. The simulator is an innovative answer and an alternate solution to the scarcity of instructional materials and devices at Caraga State University Cabadbaran Campus.
文摘Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.
文摘The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.
