A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the develo...A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.展开更多
In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges ...In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.展开更多
Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FET...Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.展开更多
In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relatio...In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.展开更多
Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful log...Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.展开更多
By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failu...By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.展开更多
The potential of all-inorganic halide perovskite-based memristors as a solution to the limitations of traditional memory systems,particularly in the context of edge computing and next-generation digital architectures,...The potential of all-inorganic halide perovskite-based memristors as a solution to the limitations of traditional memory systems,particularly in the context of edge computing and next-generation digital architectures,is investigated.The rapid expansion of data-driven applications demands more efficient,secure,and scalable memory technologies,prompting this exploration of memristors for their unique resistance-switching properties.The research aims to address the challenges of data security and processing efficiency by integrating memristors into logic circuits,enabling both memory and logic operations within a single device.The study is structured around the experimental fabrication and characterization of Cs_(3)Bi_(2)I_(6)Br_(3)perovskite memristors.A simple solution-processed spin coating method with antisolvent-assisted crystallization was employed to fabricate the memristor devices.The experimental characterization of memristors,including X-ray diffraction(XRD)analysis and electrical measurements,confirmed their structural integrity and memristive behavior,with distinct hysteresis loops indicative of non-volatile memory properties.To analyze the behavior of the memristors in electronic circuits,a Verilog-A mathematical model was developed,and simulations were conducted using the Cadence Virtuoso Electronic Design Automation(EDA)suite.The Verilog-A model demonstrates strong agreement with measured results and validates the device's hysteresis behavior.Key findings demonstrate that metal halide perovskite(MHP)memristors exhibit excellent switching characteristics,repeatability,and integration potential with complementary metal-oxide-semiconductor(CMOS)technology.These properties make them suitable for implementing various logic gates,such as IMPLY,AND,and OR gates,as well as more complex digital circuits like multiplexers and full adders.The results highlight the feasibility of using these memristors for in-memory computing,where both data storage and processing occur within the memory cells,significantly enhancing computing efficiency and security.The study concludes that MHP-based memristors offer a promising path toward more compact,energy-efficient,and secure com-puting architectures.展开更多
In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improv...In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked...First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
Ratiometric fluorescent detection of iron(Ⅲ)(Fe^(3+))offers inherent self-calibration and contactless analytic capabilities.However,realizing a dual-emission near-infrared(NIR)nanosensor with a low limit of detection...Ratiometric fluorescent detection of iron(Ⅲ)(Fe^(3+))offers inherent self-calibration and contactless analytic capabilities.However,realizing a dual-emission near-infrared(NIR)nanosensor with a low limit of detection(LOD)is rather challenging.In this work,we report the synthesis of water-dispersible erbium-hyperdoped silicon quantum dots(Si QDs:Er),which emit NIR light at the wavelengths of 810 and 1540 nm.A dual-emission NIR nanosensor based on water-dispersible Si QDs:Er enables ratiometric Fe^(3+)detection with a very low LOD(0.06μM).The effects of pH,recyclability,and the interplay between static and dynamic quenching mechanisms for Fe^(3+)detection have been systematically studied.In addition,we demonstrate that the nanosensor may be used to construct a sequential logic circuit with memory functions.展开更多
This paper discusses needs for the automation of the underdevelopment communities.The novelty of this research is the link between production of microprocessors and increasing of the life quality.This study highlights...This paper discusses needs for the automation of the underdevelopment communities.The novelty of this research is the link between production of microprocessors and increasing of the life quality.This study highlights the importance of efficient and economic architecture of logical circuits for the automation.The aim of this research is to produce a logical circuit,which includes suitable gates.The circuit will be embedded in the automatic devices as a microprocessor to cause programmed functions.This research reports analytically a workshop method to build the circuit.It uses an assembly card and required gates.Then,it suggests certain VHDL codes to drive a motor.The workshop presents the configuration schemes and connection board for every gate.In addition,it shows a schematic wiring diagram of the circuit.Finally,the economic analysis proves the mass production of the circuit will enhance the automation and consequently the quality of life.The outcome of this research is a helpful experience to the engineers,manufacturers and students of the relevant disciplines to resolve the inequality in the use of the modern technologies.展开更多
Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computin...Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.展开更多
Since the successful fabrication of two-dimensional(2D)tellurium(Te)in 2017,its fascinating properties including a thickness dependence bandgap,environmental stability,piezoelectric effect,high carrier mobility,and ph...Since the successful fabrication of two-dimensional(2D)tellurium(Te)in 2017,its fascinating properties including a thickness dependence bandgap,environmental stability,piezoelectric effect,high carrier mobility,and photoresponse among others show great potential for various applications.These include photodetectors,field-effect transistors,piezoelectric devices,modulators,and energy harvesting devices.However,as a new member of the 2D material family,much less known is about 2D Te compared to other 2D materials.Motivated by this lack of knowledge,we review the recent progress of research into 2D Te nanoflakes.Firstly,we introduce the background and motivation of this review.Then,the crystal structures and synthesis methods are presented,followed by an introduction to their physical properties and applications.Finally,the challenges and further development directions are summarized.We believe that milestone investigations of 2D Te nanoflakes will emerge soon,which will bring about great industrial revelations in 2D materials-based nanodevice commercialization.展开更多
Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enablin...Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly（1,3,5-trivinyl-l,3,5-trimethyl cyclotrisiloxane） （pV3D3）-based memristor array. Although memristive logic-in-memory circuits have been previously reported, the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only. Using memristor-aided logic （MAGIC） architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate, for the first time, we experimentally demonstrated our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within a crossbar array. This research advances the development of novel computing architecture with zero static power consumption for battery- powered flexible electronic systems.展开更多
Scaling of complementary metal-oxide-semiconductor technology nodes using conventional semiconducting materials is slowing down.The development of semiconductor technology with new materials and new concepts has becom...Scaling of complementary metal-oxide-semiconductor technology nodes using conventional semiconducting materials is slowing down.The development of semiconductor technology with new materials and new concepts has become an important focus of scientific and industrial research.In recent years,emerging ambipolar two-dimensional(2D)materials-based reconfigurable devices have shown their potential in high-integration,multifunctional circuits and have begun to attract the attention of researchers.Here,we summarize the latest progress in the field concerning ambipolar 2D materials-based reconfigurable devices.Firstly,we introduce the basic properties and preparation methods of ambipolar 2D materials.Secondly,we discuss the latest applications of reconfigurable devices based on ambipolar 2D materials.Furthermore,we also introduce the current research status of ambipolar material devices in large-scale integration.Finally,we analyze the challenges faced during the development of ambipolar 2D materials-based reconfigurable devices and provide prospects for their future development.展开更多
Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the ...Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.展开更多
Metal-oxide-semiconductor field effect transistors(MOSFET)based on two-dimensional(2D)semiconductors have attracted extensive attention owing to their excellent transport properties,atomically thin geometry,and tunabl...Metal-oxide-semiconductor field effect transistors(MOSFET)based on two-dimensional(2D)semiconductors have attracted extensive attention owing to their excellent transport properties,atomically thin geometry,and tunable bandgaps.Besides improving the transistor performance of individual device,lots of efforts have been devoted to achieving 2D logic functions or integrated circuit towards practical application.In this review,we discussed the recent progresses of 2D-based logic circuit.We will first start with the different methods for realization of n-type metal-oxide-semiconductor(NMOS)-only(or p-type metal-oxide-semiconductor(PMOS)-only)logic circuit.Next,various device polarity control and complementary-metal-oxide-semiconductor(CMOS)approaches are summarized,including utilizing different 2D semiconductors with intrinsic complementary doping,charge transfer doping,contact engineering,and electrostatics doping.We will discuss the merits and drawbacks of each approach,and lastly conclude with a short perspective on the challenges and future developments of 2D logic circuit.展开更多
The atomristor(monolayer two-dimensional(2D)-material memristor)is competitive in high-speed logic computing due to its binary feature,lower energy consumption,faster switch response,and so on.Yet to date,all-atomrist...The atomristor(monolayer two-dimensional(2D)-material memristor)is competitive in high-speed logic computing due to its binary feature,lower energy consumption,faster switch response,and so on.Yet to date,all-atomristor logic gates used for logic computing have not been reported due to the poor consistency of different atomristors in performance.Here,by studying band structures and electron transport properties of MoS2 atomristor,a comprehensive memristive mechanism is obtained.Guided by the simulation results,monolayer MoS2 with moderated defect concentration has been fabricated in the experiment,which can build atomristors with high performance and good consistency.Based on this,for the first time,MoS2 all-atomristor logic gates are realized successfully.As a demonstration,a half-adder based on the logic gates and a binary neural network(BNN)based on crossbar arrays are evaluated,indicating the applicability in various logic computing circumstances.Owing to shorter transition time and lower energy consumption,all-atomristor logic gates will open many new opportunities for next-generation logic computing and data processing.展开更多
NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-p...NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.展开更多
基金Project supported in part by the National Natural Science Foundation of China (Grant No. 61871429)the Natural Science Foundation of Zhejiang Province,China (Grant No. LY18F010012)the Project of Ministry of Science and Technology of China (Grant No. D20011)。
文摘A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.
基金Acknowledgements The authors thank the support of National Natural Science Foundation of China （Nos. 51475099 and 51432005）, Beijing Natural Science Foundation （No. 4163077）, Beijing Nova Program （No. Z171100001117054）, the Youth Innovation Promotion Association, CAS （No. 2014033）, the ＂thousands talents＂ program for the pioneer researcher and his innovation team, China, and National Key Research and Development Program of China （No.2016YFA0202704）.
文摘In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.
基金supported in part by the Hong Kong Research Impact Fund(Grant No.R6008-18)the Shen-zhen Science and Technology Innovation Commission(Grant No.SGDX2020110309460101).
文摘Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.
基金This work was supported by the National Natural Science Foundation of China (Grant No. 60025101) and in part by the National Fundamental Research Program under contract G1999032903.
文摘In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61374150 and 11271146)the State Key Program of the National Natural Science Foundation of China(Grant No.61134012)+1 种基金the Doctoral Fund of Ministry of Education of China(Grant No.20130142130012)the Science and Technology Program of Shenzhen City,China(Grant No.JCYJ20140509162710496)
文摘Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.
基金The National Natural Science Foundation of China(No.61502422)the Natural Science Foundation of Zhejiang Province(No.LY18F020028,LQ15F020006)the Natural Science Foundation of Zhejiang University of Technology(No.2014XY007)
文摘By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.
基金funded by the European Research Council(ERC)via Horizon Europe Advanced(101097688)(PeroSpiker).
文摘The potential of all-inorganic halide perovskite-based memristors as a solution to the limitations of traditional memory systems,particularly in the context of edge computing and next-generation digital architectures,is investigated.The rapid expansion of data-driven applications demands more efficient,secure,and scalable memory technologies,prompting this exploration of memristors for their unique resistance-switching properties.The research aims to address the challenges of data security and processing efficiency by integrating memristors into logic circuits,enabling both memory and logic operations within a single device.The study is structured around the experimental fabrication and characterization of Cs_(3)Bi_(2)I_(6)Br_(3)perovskite memristors.A simple solution-processed spin coating method with antisolvent-assisted crystallization was employed to fabricate the memristor devices.The experimental characterization of memristors,including X-ray diffraction(XRD)analysis and electrical measurements,confirmed their structural integrity and memristive behavior,with distinct hysteresis loops indicative of non-volatile memory properties.To analyze the behavior of the memristors in electronic circuits,a Verilog-A mathematical model was developed,and simulations were conducted using the Cadence Virtuoso Electronic Design Automation(EDA)suite.The Verilog-A model demonstrates strong agreement with measured results and validates the device's hysteresis behavior.Key findings demonstrate that metal halide perovskite(MHP)memristors exhibit excellent switching characteristics,repeatability,and integration potential with complementary metal-oxide-semiconductor(CMOS)technology.These properties make them suitable for implementing various logic gates,such as IMPLY,AND,and OR gates,as well as more complex digital circuits like multiplexers and full adders.The results highlight the feasibility of using these memristors for in-memory computing,where both data storage and processing occur within the memory cells,significantly enhancing computing efficiency and security.The study concludes that MHP-based memristors offer a promising path toward more compact,energy-efficient,and secure com-puting architectures.
文摘In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
基金supported by the National Natural Science Foundation of China(U22A2075,U20A20209)the Fundamental Research Funds for the Central Universities(226-2022-00200)the Qianjiang Distinguished Experts program of Hangzhou.
文摘Ratiometric fluorescent detection of iron(Ⅲ)(Fe^(3+))offers inherent self-calibration and contactless analytic capabilities.However,realizing a dual-emission near-infrared(NIR)nanosensor with a low limit of detection(LOD)is rather challenging.In this work,we report the synthesis of water-dispersible erbium-hyperdoped silicon quantum dots(Si QDs:Er),which emit NIR light at the wavelengths of 810 and 1540 nm.A dual-emission NIR nanosensor based on water-dispersible Si QDs:Er enables ratiometric Fe^(3+)detection with a very low LOD(0.06μM).The effects of pH,recyclability,and the interplay between static and dynamic quenching mechanisms for Fe^(3+)detection have been systematically studied.In addition,we demonstrate that the nanosensor may be used to construct a sequential logic circuit with memory functions.
文摘This paper discusses needs for the automation of the underdevelopment communities.The novelty of this research is the link between production of microprocessors and increasing of the life quality.This study highlights the importance of efficient and economic architecture of logical circuits for the automation.The aim of this research is to produce a logical circuit,which includes suitable gates.The circuit will be embedded in the automatic devices as a microprocessor to cause programmed functions.This research reports analytically a workshop method to build the circuit.It uses an assembly card and required gates.Then,it suggests certain VHDL codes to drive a motor.The workshop presents the configuration schemes and connection board for every gate.In addition,it shows a schematic wiring diagram of the circuit.Finally,the economic analysis proves the mass production of the circuit will enhance the automation and consequently the quality of life.The outcome of this research is a helpful experience to the engineers,manufacturers and students of the relevant disciplines to resolve the inequality in the use of the modern technologies.
文摘Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.
基金supported by the National Natural Science Fund of China(Grant Nos.61875138,61435010,and 61961136001)Science and Technology Innovation Commission of Shenzhen(KQJSCX20180328095501798,JCYJ20180507182047316,KQTD2015032416270385,JCYJ20170811093453105,JCYJ20180307164612205 and GJHZ20180928160209731)+1 种基金Natural Science Foundation of Guangdong Province for Distinguished Young Scholars(2018B030306038)Natural Science Foundation of SZU(No.860-000002110429).
文摘Since the successful fabrication of two-dimensional(2D)tellurium(Te)in 2017,its fascinating properties including a thickness dependence bandgap,environmental stability,piezoelectric effect,high carrier mobility,and photoresponse among others show great potential for various applications.These include photodetectors,field-effect transistors,piezoelectric devices,modulators,and energy harvesting devices.However,as a new member of the 2D material family,much less known is about 2D Te compared to other 2D materials.Motivated by this lack of knowledge,we review the recent progress of research into 2D Te nanoflakes.Firstly,we introduce the background and motivation of this review.Then,the crystal structures and synthesis methods are presented,followed by an introduction to their physical properties and applications.Finally,the challenges and further development directions are summarized.We believe that milestone investigations of 2D Te nanoflakes will emerge soon,which will bring about great industrial revelations in 2D materials-based nanodevice commercialization.
文摘Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly（1,3,5-trivinyl-l,3,5-trimethyl cyclotrisiloxane） （pV3D3）-based memristor array. Although memristive logic-in-memory circuits have been previously reported, the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only. Using memristor-aided logic （MAGIC） architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate, for the first time, we experimentally demonstrated our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within a crossbar array. This research advances the development of novel computing architecture with zero static power consumption for battery- powered flexible electronic systems.
基金supported by the National Natural Science Foundation of China(22175184 and 22105207)the CAS Project for Young Scientists in Basic Research(YSBR-053)+1 种基金the Strategic Priority Research Programme of the Chinese Academy of Sciences(XDB0520202)the CAS Project for Young Scientists in Interdisciplinary Research.
文摘Scaling of complementary metal-oxide-semiconductor technology nodes using conventional semiconducting materials is slowing down.The development of semiconductor technology with new materials and new concepts has become an important focus of scientific and industrial research.In recent years,emerging ambipolar two-dimensional(2D)materials-based reconfigurable devices have shown their potential in high-integration,multifunctional circuits and have begun to attract the attention of researchers.Here,we summarize the latest progress in the field concerning ambipolar 2D materials-based reconfigurable devices.Firstly,we introduce the basic properties and preparation methods of ambipolar 2D materials.Secondly,we discuss the latest applications of reconfigurable devices based on ambipolar 2D materials.Furthermore,we also introduce the current research status of ambipolar material devices in large-scale integration.Finally,we analyze the challenges faced during the development of ambipolar 2D materials-based reconfigurable devices and provide prospects for their future development.
基金fundings from the National Natural Science Foundation of China(Nos.62274013 and 92163206)the National Key Research and Development Program of China(No.2023YFB3405600)Science Fund for Creative Research Groups of the National Natural Science Foundation of China(No.12321004)。
文摘Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.
基金the National Natural Science Foundation of China(Nos.51991340,51991341,51802090,and 61874041)from the Hunan Science Fund for Excellent Young Scholars(No.812019037).
文摘Metal-oxide-semiconductor field effect transistors(MOSFET)based on two-dimensional(2D)semiconductors have attracted extensive attention owing to their excellent transport properties,atomically thin geometry,and tunable bandgaps.Besides improving the transistor performance of individual device,lots of efforts have been devoted to achieving 2D logic functions or integrated circuit towards practical application.In this review,we discussed the recent progresses of 2D-based logic circuit.We will first start with the different methods for realization of n-type metal-oxide-semiconductor(NMOS)-only(or p-type metal-oxide-semiconductor(PMOS)-only)logic circuit.Next,various device polarity control and complementary-metal-oxide-semiconductor(CMOS)approaches are summarized,including utilizing different 2D semiconductors with intrinsic complementary doping,charge transfer doping,contact engineering,and electrostatics doping.We will discuss the merits and drawbacks of each approach,and lastly conclude with a short perspective on the challenges and future developments of 2D logic circuit.
基金This work was supported by the National Natural Science Foundation of China(Nos.51971070,10974037,and 62205011)the National Key Research and Development Program of China(No.2016YFA0200403)+4 种基金Eu-FP7 Project(No.247644)CAS Strategy Pilot Program(No.XDA 09020300)Fundamental Research Funds for the Central Universities(No.buctrc202122)the Open Research Project of Zhejiang province Key Laboratory of Quantum Technology and Device(No.20220401)the Open Research Project of Special Display and Imaging Technology Innovation Center of Anhui Province(No.2022AJ05001).
文摘The atomristor(monolayer two-dimensional(2D)-material memristor)is competitive in high-speed logic computing due to its binary feature,lower energy consumption,faster switch response,and so on.Yet to date,all-atomristor logic gates used for logic computing have not been reported due to the poor consistency of different atomristors in performance.Here,by studying band structures and electron transport properties of MoS2 atomristor,a comprehensive memristive mechanism is obtained.Guided by the simulation results,monolayer MoS2 with moderated defect concentration has been fabricated in the experiment,which can build atomristors with high performance and good consistency.Based on this,for the first time,MoS2 all-atomristor logic gates are realized successfully.As a demonstration,a half-adder based on the logic gates and a binary neural network(BNN)based on crossbar arrays are evaluated,indicating the applicability in various logic computing circumstances.Owing to shorter transition time and lower energy consumption,all-atomristor logic gates will open many new opportunities for next-generation logic computing and data processing.
基金supported by the National Natural Science Foundation of China(Nos.61274036,61106038,61371025)the Doctoral Fund of Ministry of Education of China(No.20110111120012)
文摘NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.
