A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the develo...A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.展开更多
The potential of all-inorganic halide perovskite-based memristors as a solution to the limitations of traditional memory systems,particularly in the context of edge computing and next-generation digital architectures,...The potential of all-inorganic halide perovskite-based memristors as a solution to the limitations of traditional memory systems,particularly in the context of edge computing and next-generation digital architectures,is investigated.The rapid expansion of data-driven applications demands more efficient,secure,and scalable memory technologies,prompting this exploration of memristors for their unique resistance-switching properties.The research aims to address the challenges of data security and processing efficiency by integrating memristors into logic circuits,enabling both memory and logic operations within a single device.The study is structured around the experimental fabrication and characterization of Cs_(3)Bi_(2)I_(6)Br_(3)perovskite memristors.A simple solution-processed spin coating method with antisolvent-assisted crystallization was employed to fabricate the memristor devices.The experimental characterization of memristors,including X-ray diffraction(XRD)analysis and electrical measurements,confirmed their structural integrity and memristive behavior,with distinct hysteresis loops indicative of non-volatile memory properties.To analyze the behavior of the memristors in electronic circuits,a Verilog-A mathematical model was developed,and simulations were conducted using the Cadence Virtuoso Electronic Design Automation(EDA)suite.The Verilog-A model demonstrates strong agreement with measured results and validates the device's hysteresis behavior.Key findings demonstrate that metal halide perovskite(MHP)memristors exhibit excellent switching characteristics,repeatability,and integration potential with complementary metal-oxide-semiconductor(CMOS)technology.These properties make them suitable for implementing various logic gates,such as IMPLY,AND,and OR gates,as well as more complex digital circuits like multiplexers and full adders.The results highlight the feasibility of using these memristors for in-memory computing,where both data storage and processing occur within the memory cells,significantly enhancing computing efficiency and security.The study concludes that MHP-based memristors offer a promising path toward more compact,energy-efficient,and secure com-puting architectures.展开更多
By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failu...By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked...First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunnelin...The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.展开更多
The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits...The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.展开更多
As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design f...As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.展开更多
In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS...In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.展开更多
Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of ...Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of physical experiments and decrease instrument damage caused by operating errors.CircuitVerse is an open-source and Web-based tool of circuit design and simulation for teaching purposes.And now,teachers and students in many colleges and universities use it to assist teaching and learning.Firstly,through a particular example,the features of CircuitVerse and its usage are explained.Secondly,we briefly introduce the application of CircuitVerse in our teaching as well as the following development plans.We believe that our introduction can help teachers understand the software and how to make full use of this tool.展开更多
The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital de...The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.展开更多
Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FET...Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.展开更多
The inclusion of the human rights clause in the Chi-nese Constitution is a concern and expression of the spirit of the Con-stitution,which has laid the institutional regulations of the fundamen-tal law for the develop...The inclusion of the human rights clause in the Chi-nese Constitution is a concern and expression of the spirit of the Con-stitution,which has laid the institutional regulations of the fundamen-tal law for the development of human rights in China,provided the principles and value norms of the highest level of effectiveness for the legal protection of human rights,and built a profound constitutional basis for the formation and improvement of the Chinese path of human rights development.The human rights clause is not only a summariza-tion and affirmation of the historical practice of Chinese human rights development under the leadership of the Communist Party of China,but also a new starting point for the development of human rights in China under the leadership of the Communist Party of China.It marks that the development of human rights in China has entered a new era.The Party and the state have finally embarked on a path of human rights development with Chinese characteristics by formulating and implementing the Human Rights Action Plan of China,eliminating ab-solute poverty through the national poverty alleviation campaign,and promoting human rights protection through the rule of law.展开更多
In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges ...In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.展开更多
Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful log...Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.展开更多
In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relatio...In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.展开更多
Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also propose...Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.展开更多
Soccer robot system is a tremendously challenging intelligent system developed to mimic human soccer competition based on the multi discipline research: robotics, intelligent control, computer vision, etc. robot path ...Soccer robot system is a tremendously challenging intelligent system developed to mimic human soccer competition based on the multi discipline research: robotics, intelligent control, computer vision, etc. robot path planning strategy is a very important subject concerning to the performance and intelligence degree of the multi robot system. Therefore, this paper studies the path planning strategy of soccer system by using fuzzy logic. After setting up two fuzziers and two sorts of fuzzy rules for soccer system, fuzzy logic is applied to workspace partition and path revision. The experiment results show that this technique can well enhance the performance and intelligence degree of the system.展开更多
Delay optimization has recently attracted signif-icant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient...Delay optimization has recently attracted signif-icant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient delay op-timization approach (EDOA) for MPRM logic circuits under the unit delay model, which can derive an optimal MPRM logic circuit with minimum delay. First, the simplest MPRM expression with the fewest number of product terms is ob-tained using a novel Reed-Muller expression simplification approach (RMESA) considering don't-care terms. Second, a minimum delay decomposition approach based on a Huffman tree construction algorithm is utilized on the simplest MPRM expression. Experimental results on MCNC benchmark cir-cuits demonstrate that compared to the Berkeley SIS 1.2 and ABC, the EDOA can significantly reduce delay for most cir-cuits. Furthermore, for a few circuits, while reducing delay, the EDOA incurs an area penalty.展开更多
Since Moore's Law was proposed in the 1970s, the size of silicon(Si) transistors has continuously shrunk, significantly increasing the integration density and computational power of integrated circuits [1].
基金Project supported in part by the National Natural Science Foundation of China (Grant No. 61871429)the Natural Science Foundation of Zhejiang Province,China (Grant No. LY18F010012)the Project of Ministry of Science and Technology of China (Grant No. D20011)。
文摘A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.
基金funded by the European Research Council(ERC)via Horizon Europe Advanced(101097688)(PeroSpiker).
文摘The potential of all-inorganic halide perovskite-based memristors as a solution to the limitations of traditional memory systems,particularly in the context of edge computing and next-generation digital architectures,is investigated.The rapid expansion of data-driven applications demands more efficient,secure,and scalable memory technologies,prompting this exploration of memristors for their unique resistance-switching properties.The research aims to address the challenges of data security and processing efficiency by integrating memristors into logic circuits,enabling both memory and logic operations within a single device.The study is structured around the experimental fabrication and characterization of Cs_(3)Bi_(2)I_(6)Br_(3)perovskite memristors.A simple solution-processed spin coating method with antisolvent-assisted crystallization was employed to fabricate the memristor devices.The experimental characterization of memristors,including X-ray diffraction(XRD)analysis and electrical measurements,confirmed their structural integrity and memristive behavior,with distinct hysteresis loops indicative of non-volatile memory properties.To analyze the behavior of the memristors in electronic circuits,a Verilog-A mathematical model was developed,and simulations were conducted using the Cadence Virtuoso Electronic Design Automation(EDA)suite.The Verilog-A model demonstrates strong agreement with measured results and validates the device's hysteresis behavior.Key findings demonstrate that metal halide perovskite(MHP)memristors exhibit excellent switching characteristics,repeatability,and integration potential with complementary metal-oxide-semiconductor(CMOS)technology.These properties make them suitable for implementing various logic gates,such as IMPLY,AND,and OR gates,as well as more complex digital circuits like multiplexers and full adders.The results highlight the feasibility of using these memristors for in-memory computing,where both data storage and processing occur within the memory cells,significantly enhancing computing efficiency and security.The study concludes that MHP-based memristors offer a promising path toward more compact,energy-efficient,and secure com-puting architectures.
基金The National Natural Science Foundation of China(No.61502422)the Natural Science Foundation of Zhejiang Province(No.LY18F020028,LQ15F020006)the Natural Science Foundation of Zhejiang University of Technology(No.2014XY007)
文摘By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
文摘The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.
基金Supported by the National Natural Science Foundation of China (No.60006002) Education Department of Guangdong Province of China (No. Z02019)
文摘The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.
文摘As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.
文摘In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.
基金This work is supported in part by the Education and Teaching Reform Project of Xidian University(A21004)the New Experimental Equipment Development Project of Xidian University(YQ21003K).
文摘Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of physical experiments and decrease instrument damage caused by operating errors.CircuitVerse is an open-source and Web-based tool of circuit design and simulation for teaching purposes.And now,teachers and students in many colleges and universities use it to assist teaching and learning.Firstly,through a particular example,the features of CircuitVerse and its usage are explained.Secondly,we briefly introduce the application of CircuitVerse in our teaching as well as the following development plans.We believe that our introduction can help teachers understand the software and how to make full use of this tool.
文摘The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.
基金supported in part by the Hong Kong Research Impact Fund(Grant No.R6008-18)the Shen-zhen Science and Technology Innovation Commission(Grant No.SGDX2020110309460101).
文摘Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.
基金the Research on Building a Theoretical System of Constitutional Supervision with Chinese Char-acteristics(Project Approval Number 23JDZ025)a major research project of the Ministry of Education in Philosophy and Social Sciences.
文摘The inclusion of the human rights clause in the Chi-nese Constitution is a concern and expression of the spirit of the Con-stitution,which has laid the institutional regulations of the fundamen-tal law for the development of human rights in China,provided the principles and value norms of the highest level of effectiveness for the legal protection of human rights,and built a profound constitutional basis for the formation and improvement of the Chinese path of human rights development.The human rights clause is not only a summariza-tion and affirmation of the historical practice of Chinese human rights development under the leadership of the Communist Party of China,but also a new starting point for the development of human rights in China under the leadership of the Communist Party of China.It marks that the development of human rights in China has entered a new era.The Party and the state have finally embarked on a path of human rights development with Chinese characteristics by formulating and implementing the Human Rights Action Plan of China,eliminating ab-solute poverty through the national poverty alleviation campaign,and promoting human rights protection through the rule of law.
基金Acknowledgements The authors thank the support of National Natural Science Foundation of China （Nos. 51475099 and 51432005）, Beijing Natural Science Foundation （No. 4163077）, Beijing Nova Program （No. Z171100001117054）, the Youth Innovation Promotion Association, CAS （No. 2014033）, the ＂thousands talents＂ program for the pioneer researcher and his innovation team, China, and National Key Research and Development Program of China （No.2016YFA0202704）.
文摘In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61374150 and 11271146)the State Key Program of the National Natural Science Foundation of China(Grant No.61134012)+1 种基金the Doctoral Fund of Ministry of Education of China(Grant No.20130142130012)the Science and Technology Program of Shenzhen City,China(Grant No.JCYJ20140509162710496)
文摘Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.
基金This work was supported by the National Natural Science Foundation of China (Grant No. 60025101) and in part by the National Fundamental Research Program under contract G1999032903.
文摘In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.
文摘Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.
文摘Soccer robot system is a tremendously challenging intelligent system developed to mimic human soccer competition based on the multi discipline research: robotics, intelligent control, computer vision, etc. robot path planning strategy is a very important subject concerning to the performance and intelligence degree of the multi robot system. Therefore, this paper studies the path planning strategy of soccer system by using fuzzy logic. After setting up two fuzziers and two sorts of fuzzy rules for soccer system, fuzzy logic is applied to workspace partition and path revision. The experiment results show that this technique can well enhance the performance and intelligence degree of the system.
基金This work was supported by the National Natural Science Foundation of China (Grant Nos. 61370059 and 61232009)Beijing Natural Science Foundation (4152030), Fundamental Research Funds for the Central Universities (YWF-15-GJSYS-085, YWF-14-JSJXY-14)+1 种基金Open Project Program of National Engineering Research Center for Science & Technology Resources Sharing Service (Beihang University), the fund of the State Key Laboratory of Computer Architecture (CARCH201507)the fund of the State Key Laboratory of Software Development Environment (SKLSDE-2016ZX-13).
文摘Delay optimization has recently attracted signif-icant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient delay op-timization approach (EDOA) for MPRM logic circuits under the unit delay model, which can derive an optimal MPRM logic circuit with minimum delay. First, the simplest MPRM expression with the fewest number of product terms is ob-tained using a novel Reed-Muller expression simplification approach (RMESA) considering don't-care terms. Second, a minimum delay decomposition approach based on a Huffman tree construction algorithm is utilized on the simplest MPRM expression. Experimental results on MCNC benchmark cir-cuits demonstrate that compared to the Berkeley SIS 1.2 and ABC, the EDOA can significantly reduce delay for most cir-cuits. Furthermore, for a few circuits, while reducing delay, the EDOA incurs an area penalty.
文摘Since Moore's Law was proposed in the 1970s, the size of silicon(Si) transistors has continuously shrunk, significantly increasing the integration density and computational power of integrated circuits [1].
