The microwave plasma oxidation under the relatively high pressure(6 kPa)region is introduced into the fabrication process of SiO_(2)/4 H-SiC stack.By controlling the oxidation pressure,species,and temperature,the reco...The microwave plasma oxidation under the relatively high pressure(6 kPa)region is introduced into the fabrication process of SiO_(2)/4 H-SiC stack.By controlling the oxidation pressure,species,and temperature,the record low density of interface traps(~4×10^(10)cm^(-2)·eV^(-1)@Ec-0.2 eV)is demonstrated on SiO_(2)/SiC stack formed by microwave plasma oxidation.And high quality SiO_(2)with very flat interface(0.27-nm root-mean-square roughness)is obtained.High performance Si C metal–oxide–semiconductor field-effect transistors(MOSFETs)with peak field effect mobility of 44 cm^(-2)·eV^(-1)is realized without additional treatment.These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.展开更多
Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give ...Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of △Nit-t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.展开更多
The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method dir...The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.展开更多
Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the princi...Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.展开更多
The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simu...The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.展开更多
The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is me...The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.展开更多
The effects of wet re-oxidation annealing （wet-ROA） on the shallow interface traps of n-type 4H-SiC metal oxide-semiconductor （MOS） capacitors were investigated by Gray-Brown method and angle-dependent X- ray phot...The effects of wet re-oxidation annealing （wet-ROA） on the shallow interface traps of n-type 4H-SiC metal oxide-semiconductor （MOS） capacitors were investigated by Gray-Brown method and angle-dependent X- ray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps （Dit） from 0 to 0.2 eV below SiC conduction band edge （Ec） of the sample with wet-ROA for the first time, and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species, which results in C release and SiOxCy transformation into higher oxidation states, thus reducing the SiOxCy content and the SiOxCy interface transition region thickness.展开更多
Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interfa...Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 10^12 cm^−2 and 6.35 × 10^12 cm^−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.展开更多
According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9n...According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm MOSFET.And thus the energy distribution of interface trap can be determined.According to the two methods,the energy profile of interface traps agrees with those reported in literature.Compared to other methods,this method is simpler and more convenient.展开更多
Effective improvement in electrical properties of NO passivated SiC/SiO2 interface after being irradiated by electrons is demonstrated.The density of interface traps after being irradiated by 100-kGy electrons decreas...Effective improvement in electrical properties of NO passivated SiC/SiO2 interface after being irradiated by electrons is demonstrated.The density of interface traps after being irradiated by 100-kGy electrons decreases by about one order of magnitude,specifically,from 3×1012 cm-2·eV-1 to 4×1011 cm-2·eV-1 at 0.2 eV below the conduction band of 4H-SiC without any degradation of electric breakdown field.Particularly,the results of x-ray photoelectron spectroscopy measurement show that the C-N bonds are generated near the interface after electron irradiation,indicating that the carbon-related defects are further reduced.展开更多
Strained germanium hole spin qubits are promising for quantum computing,but the devices hosting these qubits face challenges from high interface trap density,which originates from the naturally oxidized surface of the...Strained germanium hole spin qubits are promising for quantum computing,but the devices hosting these qubits face challenges from high interface trap density,which originates from the naturally oxidized surface of the wafer.These traps can degrade the device stability and cause an excessively high threshold voltage.Surface passivation is regarded as an effective method to mitigate these impacts.In this study,we perform low-thermal-budget chemical passivation using the nitric acid oxidation of silicon method on the surface of strained germanium devices and investigate the impact of passivation on the device stability.The results demonstrate that surface passivation effectively reduces the interface defect density.This not only improves the stability of the device's threshold voltage but also enhances its long-term static stability.Furthermore,we construct a band diagram of hole surface tunneling at the static operating point to gain a deeper understanding of the physical mechanism through which passivation affects the device stability.This study provides valuable insights for future optimization of strained Ge-based quantum devices and advances our understanding of how interface states affect device stability.展开更多
A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degr...A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.展开更多
This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is...This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.展开更多
The interface state of hydrogen-terminated(C-H)diamond metal-oxide-semiconductor field-effect transistor(MOSFET)is critical for device performance.In this paper,we investigate the fixed charges and interface trap stat...The interface state of hydrogen-terminated(C-H)diamond metal-oxide-semiconductor field-effect transistor(MOSFET)is critical for device performance.In this paper,we investigate the fixed charges and interface trap states in C-H diamond MOSFETs by using different gate dielectric processes.The devices use Al_(2)O_(3) as gate dielectrics that are deposited via atomic layer deposition(ALD)at 80℃and 300℃,respectively,and their C-V and I-V characteristics are comparatively investigated.Mott-Schottky plots(1/C2-VG)suggest that positive and negative fixed charges with low density of about 10^(11)cm^(-2) are located in the 80-℃-and 300-℃deposition Al2O3 films,respectively.The analyses of direct current(DC)/pulsed I-V and frequency-dependent conductance show that the shallow interface traps(0.46 eV-0.52 eV and 0.53 eV-0.56 eV above the valence band of diamond for the 80-℃and 300-℃deposition conditions,respectively)with distinct density(7.8×10^(13)eV^(-1)·cm^(-2)-8.5×10^(13)eV^(-1)·cm^(-2) and 2.2×10^(13)eV^(-1)·cm^(-2)-5.1×10^(13)eV^(-1)·cm^(-2) for the 80-℃-and 300-℃-deposition conditions,respectively)are present at the Al2O3/C-H diamond interface.Dynamic pulsed I-V and capacitance dispersion results indicate that the ALD Al_(2)O_(3) technique with 300-℃deposition temperature has higher stability for C-H diamond MOSFETs.展开更多
The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias s...The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.展开更多
ZnO-based thin film transistors(TFTs)with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density.In this work,we fabricated Hf-doped ZnO films with different cycle ratio o...ZnO-based thin film transistors(TFTs)with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density.In this work,we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment.The results show that the cycle ratio of Zn/Hf is optimized to be 10:1,and the corresponding atomic ratio is 2.24%.The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases,owning to the decrease of the oxygen vacancies and interface trap density.Furthermore,we developed Hf-doped ZnO TFT with high bias stability by introducing HfO_(2)intermediate layer between the active layer and SiO_(2)dielectric layer,and the shift of threshold voltage is as low as-0.273 V,showing high bias stability.Also,the device has the high field-effective mobility of 52.4 cm^(2)/Vs,low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6×10^(8).The results indicate a promising fabrication method for highperformance ZnO-based TFTs,which may be applied in logic circuits,radio frequency identification and so on.展开更多
Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）....Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.展开更多
A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structur...A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structure. In this model, the influences of interface trap charge （ITC） at the Si-SiO2 interface and fixed oxide charge （FOC） in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.展开更多
Frequency dependent conductance measurements are implemented to investigate the interface states in Al2O3/A1GaN/GaN metal-oxide-semiconductor （MOS） structures. Two types of device structures, namely, the recessed ga...Frequency dependent conductance measurements are implemented to investigate the interface states in Al2O3/A1GaN/GaN metal-oxide-semiconductor （MOS） structures. Two types of device structures, namely, the recessed gate structure （RGS） and the normal gate structure （NGS）, are studied in the experiment. Interface trap parameters includ-ing trap density Dit, trap time constant ιit, and trap state energy ET in both devices have been determined. Furthermore, the obtained results demonstrate that the gate recess process can induce extra traps with shallower energy levels at the Al2O3/AlGaN interface due to the damage on the surface of the AlGaN barrier layer resulting from reactive ion etching （RIE）.展开更多
CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in t...CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.展开更多
基金Project supported in part by the National Key Research and Development Program of China(Grant No.2016YFB0100601)the National Natural Science Foundation of China(Grant Nos.61674169 and 61974159)the Support from a Grant-In-Aid from the Youth Innovation Promotion Association of the Chinese Academy of Sciences。
文摘The microwave plasma oxidation under the relatively high pressure(6 kPa)region is introduced into the fabrication process of SiO_(2)/4 H-SiC stack.By controlling the oxidation pressure,species,and temperature,the record low density of interface traps(~4×10^(10)cm^(-2)·eV^(-1)@Ec-0.2 eV)is demonstrated on SiO_(2)/SiC stack formed by microwave plasma oxidation.And high quality SiO_(2)with very flat interface(0.27-nm root-mean-square roughness)is obtained.High performance Si C metal–oxide–semiconductor field-effect transistors(MOSFETs)with peak field effect mobility of 44 cm^(-2)·eV^(-1)is realized without additional treatment.These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.
基金Sponsored by Motorola-Peking University Joint Project.Contract No.:MSPSDDLCHINA-0004
文摘Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of △Nit-t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.
基金special funds of major state basic research projects (G20000365)
文摘The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.
基金Project Supported by Motorola CPT(Contract No.MSPSESTL-CTC9903)
文摘Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant No.61106106)the Fundamental Research Funds for the Central Universities,China(Grant No.K50511250008)
文摘The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.
文摘The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.
基金Project supported by the Fundamental Research Funds for the Central Universities,Ministry of Education,China(No.DUT11ZD114)
文摘The effects of wet re-oxidation annealing （wet-ROA） on the shallow interface traps of n-type 4H-SiC metal oxide-semiconductor （MOS） capacitors were investigated by Gray-Brown method and angle-dependent X- ray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps （Dit） from 0 to 0.2 eV below SiC conduction band edge （Ec） of the sample with wet-ROA for the first time, and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species, which results in C release and SiOxCy transformation into higher oxidation states, thus reducing the SiOxCy content and the SiOxCy interface transition region thickness.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61704124, 11690042, and 61634005).
文摘Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 10^12 cm^−2 and 6.35 × 10^12 cm^−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.
文摘According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm MOSFET.And thus the energy distribution of interface trap can be determined.According to the two methods,the energy profile of interface traps agrees with those reported in literature.Compared to other methods,this method is simpler and more convenient.
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFB0100601)the National Natural Science Foundation of China(Grant Nos.61674169 and 61974159).
文摘Effective improvement in electrical properties of NO passivated SiC/SiO2 interface after being irradiated by electrons is demonstrated.The density of interface traps after being irradiated by 100-kGy electrons decreases by about one order of magnitude,specifically,from 3×1012 cm-2·eV-1 to 4×1011 cm-2·eV-1 at 0.2 eV below the conduction band of 4H-SiC without any degradation of electric breakdown field.Particularly,the results of x-ray photoelectron spectroscopy measurement show that the C-N bonds are generated near the interface after electron irradiation,indicating that the carbon-related defects are further reduced.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.92265113,12034018,12474490,and 62404248)the Innovation Program for Quantum Science and Technology(Grant No.2021ZD0302300)。
文摘Strained germanium hole spin qubits are promising for quantum computing,but the devices hosting these qubits face challenges from high interface trap density,which originates from the naturally oxidized surface of the wafer.These traps can degrade the device stability and cause an excessively high threshold voltage.Surface passivation is regarded as an effective method to mitigate these impacts.In this study,we perform low-thermal-budget chemical passivation using the nitric acid oxidation of silicon method on the surface of strained germanium devices and investigate the impact of passivation on the device stability.The results demonstrate that surface passivation effectively reduces the interface defect density.This not only improves the stability of the device's threshold voltage but also enhances its long-term static stability.Furthermore,we construct a band diagram of hole surface tunneling at the static operating point to gain a deeper understanding of the physical mechanism through which passivation affects the device stability.This study provides valuable insights for future optimization of strained Ge-based quantum devices and advances our understanding of how interface states affect device stability.
文摘A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.
文摘This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.
基金the National Natural Science Foundation of China(Grant No.61922021)the National Key Research and Development Project,China(Grant No.2018YFE0115500)the Fund from the Sichuan Provincial Engineering Research Center for Broadband Microwave Circuit High Density Integration,China.
文摘The interface state of hydrogen-terminated(C-H)diamond metal-oxide-semiconductor field-effect transistor(MOSFET)is critical for device performance.In this paper,we investigate the fixed charges and interface trap states in C-H diamond MOSFETs by using different gate dielectric processes.The devices use Al_(2)O_(3) as gate dielectrics that are deposited via atomic layer deposition(ALD)at 80℃and 300℃,respectively,and their C-V and I-V characteristics are comparatively investigated.Mott-Schottky plots(1/C2-VG)suggest that positive and negative fixed charges with low density of about 10^(11)cm^(-2) are located in the 80-℃-and 300-℃deposition Al2O3 films,respectively.The analyses of direct current(DC)/pulsed I-V and frequency-dependent conductance show that the shallow interface traps(0.46 eV-0.52 eV and 0.53 eV-0.56 eV above the valence band of diamond for the 80-℃and 300-℃deposition conditions,respectively)with distinct density(7.8×10^(13)eV^(-1)·cm^(-2)-8.5×10^(13)eV^(-1)·cm^(-2) and 2.2×10^(13)eV^(-1)·cm^(-2)-5.1×10^(13)eV^(-1)·cm^(-2) for the 80-℃-and 300-℃-deposition conditions,respectively)are present at the Al2O3/C-H diamond interface.Dynamic pulsed I-V and capacitance dispersion results indicate that the ALD Al_(2)O_(3) technique with 300-℃deposition temperature has higher stability for C-H diamond MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61404098 and 61274079)the Doctoral Fund of Ministry of Education of China(Grant No.20130203120017)+2 种基金the National Key Basic Research Program of China(Grant No.2015CB759600)the National Grid Science&Technology Project,China(Grant No.SGRI-WD-71-14-018)the Key Specific Project in the National Science&Technology Program,China(Grant Nos.2013ZX02305002-002 and 2015CB759600)
文摘The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.
基金the National Key R&D Program of China(No.2020YFB2008701)。
文摘ZnO-based thin film transistors(TFTs)with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density.In this work,we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment.The results show that the cycle ratio of Zn/Hf is optimized to be 10:1,and the corresponding atomic ratio is 2.24%.The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases,owning to the decrease of the oxygen vacancies and interface trap density.Furthermore,we developed Hf-doped ZnO TFT with high bias stability by introducing HfO_(2)intermediate layer between the active layer and SiO_(2)dielectric layer,and the shift of threshold voltage is as low as-0.273 V,showing high bias stability.Also,the device has the high field-effective mobility of 52.4 cm^(2)/Vs,low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6×10^(8).The results indicate a promising fabrication method for highperformance ZnO-based TFTs,which may be applied in logic circuits,radio frequency identification and so on.
基金supported by the National Basic Research Program of China(Grant No.2011CBA00601)the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2009ZX02035-001)the National Natural Science Foundation of China(Grant Nos.60625403,60806033,and 60925015)
文摘Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.
基金Project supported by the National Natural Science Foundation of China (Grant No. 61076055)the Program for Innovative Research Team of Zhejiang Normal University of China (Grant No. 2007XCXTD-5)the Open Program of Surface Physics Laboratory of Fudan University, China (Grant No. FDSKL2011-04)
文摘A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structure. In this model, the influences of interface trap charge （ITC） at the Si-SiO2 interface and fixed oxide charge （FOC） in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)
文摘Frequency dependent conductance measurements are implemented to investigate the interface states in Al2O3/A1GaN/GaN metal-oxide-semiconductor （MOS） structures. Two types of device structures, namely, the recessed gate structure （RGS） and the normal gate structure （NGS）, are studied in the experiment. Interface trap parameters includ-ing trap density Dit, trap time constant ιit, and trap state energy ET in both devices have been determined. Furthermore, the obtained results demonstrate that the gate recess process can induce extra traps with shallower energy levels at the Al2O3/AlGaN interface due to the damage on the surface of the AlGaN barrier layer resulting from reactive ion etching （RIE）.
基金supported by the National Natural Science Foundation of China(62171172).
文摘CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.
