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CMOS compatible multi-state memristor for neuromorphic hardware encryption with low operation voltage
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作者 Bo Sun Jinhao Zhang +4 位作者 Jieru Song Jialin Meng David Wei Zhang Tianyu Wang Lin Chen 《InfoMat》 2025年第11期44-53,共10页
Different from traditional software encryption,hardware encryption shows obvious advantages in AI information encryption application scenarios with high reliability and high security requirements.With the development ... Different from traditional software encryption,hardware encryption shows obvious advantages in AI information encryption application scenarios with high reliability and high security requirements.With the development of memristors,memristor-based hardware encryption attracted the interests of researchers in secure communication.Hafnium-based memristors have received widespread attention due to fast speed,low power consumption,and compatibility with CMOS technology.In this study,a HfAlOx-based memristor with an ON/OFF ratio of>104,an endurance characteristic of 105 cycles,and a low operating voltage of 0.56 V/−0.135 V was proposed.Eight-level states were achieved and used to design a hardware encryption scheme through a neural network.Parallel information encryption operations of“S”“D”“U”were realized in a memristor array.By constructing an artificial neural network,the recognition rate of encrypted letters without/with memristor is 62.3%and 98.1%,respectively.The memristor-based encryption scheme further expands the choices and application prospects of hardware encryption. 展开更多
关键词 hardware encryption lowoperationvoltage MEMRISTOR multilevelstorage neuromorphic computing
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A Novel Pipelining Encryption Hardware System with High Throughput and High Integration for 5G
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作者 Yuntao Liu Zesheng Shen +1 位作者 Shuo Fang Yun Wang 《China Communications》 SCIE CSCD 2022年第6期1-10,共10页
This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline ... This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network. 展开更多
关键词 encryption hardware system for 5G ZUC-256 stream cipher algorithm pipeline scheme throughput rate integration rate
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