As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM c...As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM cells based on conventional silicon-based devices suffer from structural complexity and large footprintlimitations. Here, we demonstrate an ultrafast nonvolatile TCAM cell based on the MoTe2/hBN/multilayergraphene (MLG) van der Waals heterostructure using a top-gated partial floating-gate field-effect transistor(PFGFET) architecture. Based on its ambipolar transport properties, the carrier type in the source/drain andcentral channel regions of the MoTe2 channel can be efficiently tuned by the control gate and top gate, respectively,enabling the reconfigurable operation of the device in either memory or FET mode. When working inthe memory mode, it achieves an ultrafast 60 ns programming/erase speed with a current on-off ratio of ∼105,excellent retention capability, and robust endurance. When serving as a reconfigurable transistor, unipolar p-typeand n-type FETs are obtained by adopting ultrafast 60 ns control-gate voltage pulses with different polarities.The monolithic integration of memory and logic within a single device enables the content-addressable memory(CAM) functionality. Finally, by integrating two PFGFETs in parallel, a TCAM cell with a high current ratioof ∼10^(5) between the match and mismatch states is achieved without requiring additional peripheral circuitry.These results provide a promising route for the design of high-performance TCAM devices for future in-memorycomputing applications.展开更多
The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number o...The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.展开更多
A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations f...A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.展开更多
AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of...AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.展开更多
A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structur...A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.展开更多
In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethac...In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethacrylate,and pentacene are used as a floating-gate layer,tunneling layer,and active layer,respectively.The device shows bidirectional storage characteristics under the action of programming/erasing(P/E)operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate.The carrier mobility and switching current ratio(Ion/Ioff ratio)of the device with a tunneling layer thickness of 85 nm are 0.01 cm^2·V^-1·s^-1 and 102,respectively.A large memory window of 9.28 V can be obtained under a P/E voltage of±60 V.展开更多
This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,...This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.展开更多
Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed an...Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.展开更多
In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness a...In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.展开更多
A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image ...A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.展开更多
The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hystere...The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.展开更多
A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is exp...A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.展开更多
Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory.However,the memory performance of the devices utilizing the same two-dimensional hetero...Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory.However,the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab,which is often attributed to variations in material thickness or interface quality without a detailed exploration.Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory.Here,we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions.For the first time,the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated.Moreover,controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated.The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.展开更多
With the explosive expansion of information,there is a growing need for non-volatile memories with high storage density and reconfigurability.Emerging two-dimensional(2D)ferroelectric materials enable the design of va...With the explosive expansion of information,there is a growing need for non-volatile memories with high storage density and reconfigurability.Emerging two-dimensional(2D)ferroelectric materials enable the design of various high-performance functional devices that can potentially address these challenges.Here,we report a ferroelectric semiconductor floating-gate transistor based on an α-In_(2)Se_(3)/hexagonal boron nitride(h-BN)/multi-layered graphene(MLG)van der Waals heterostructure on a SiO_(2)/Si substrate.Thanks to the coexistence of both out-of-plane and in-plane polarizations in an α-In_(2)Se_(3) channel,pairs of polarization-modulated channel resistance states can be successfully generated between the floating-gate-modulated on and off states,which can be programmed by either vertical gate pulses or planar drain pulses.These features enable a 2-bit multi-level memory in both three-terminal or two-terminal operational modes,significantly increasing the storage density and reconfigurability.The present results introduce a new design degree of freedom for floating-gate memories and provide fresh insights into future non-volatile memory technologies.展开更多
基金supported by the National Key Research&Development Projects of China(Grant No.2022YFA1204100)National Natural Science Foundation of China(Grant No.62488201)+1 种基金CAS Project for Young Scientists in Basic Research(YSBR-003)the Innovation Program of Quantum Science and Technology(2021ZD0302700)。
文摘As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM cells based on conventional silicon-based devices suffer from structural complexity and large footprintlimitations. Here, we demonstrate an ultrafast nonvolatile TCAM cell based on the MoTe2/hBN/multilayergraphene (MLG) van der Waals heterostructure using a top-gated partial floating-gate field-effect transistor(PFGFET) architecture. Based on its ambipolar transport properties, the carrier type in the source/drain andcentral channel regions of the MoTe2 channel can be efficiently tuned by the control gate and top gate, respectively,enabling the reconfigurable operation of the device in either memory or FET mode. When working inthe memory mode, it achieves an ultrafast 60 ns programming/erase speed with a current on-off ratio of ∼105,excellent retention capability, and robust endurance. When serving as a reconfigurable transistor, unipolar p-typeand n-type FETs are obtained by adopting ultrafast 60 ns control-gate voltage pulses with different polarities.The monolithic integration of memory and logic within a single device enables the content-addressable memory(CAM) functionality. Finally, by integrating two PFGFETs in parallel, a TCAM cell with a high current ratioof ∼10^(5) between the match and mismatch states is achieved without requiring additional peripheral circuitry.These results provide a promising route for the design of high-performance TCAM devices for future in-memorycomputing applications.
基金Project supported financially by the National Natural Science Foundation of China(Grant No.62174150)the Natural Science Foundation of Jiangsu Province,China(Grant No.BK20211040)。
文摘The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.
文摘A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11174182,11574182,and 61674130)
文摘AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.
基金Project supported by“Efficient and Energy-Saving GaN on Si Power Devices”Research Fund(Grant No.KQCX20140522151322946)the Research Fund of the Third Generation Semiconductor Key Laboratory of Shenzhen,China(Grant No.ZDSYS20140509142721434)+1 种基金the“Key Technology Research of GaN on Si Power Devices”Research Fund(Grant No.JSGG20140729145956266)the“Research of Low Cost Fabrication of GaN Power Devices and System Integration”Research Fund(Grant No.JCYJ201602261926390)
文摘A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.
文摘In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethacrylate,and pentacene are used as a floating-gate layer,tunneling layer,and active layer,respectively.The device shows bidirectional storage characteristics under the action of programming/erasing(P/E)operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate.The carrier mobility and switching current ratio(Ion/Ioff ratio)of the device with a tunneling layer thickness of 85 nm are 0.01 cm^2·V^-1·s^-1 and 102,respectively.A large memory window of 9.28 V can be obtained under a P/E voltage of±60 V.
文摘This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.
文摘Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
文摘In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
文摘A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.
基金Project supported by the TCAD Simulation and SPICE Modeling of 0.13μm SOI Technology,China (Grant No. 2009ZX02306-002)
文摘The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.
基金This work was supported by the National Nature Science Foundation of China under Grant No.60436030.
文摘A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.
基金supported by Beijing Natural Science Foundation(Grant No.Z210006)National Key R&D Plan(2022YFA1405600)National Natural Science Foundation of China(Grant No.12104051).
文摘Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory.However,the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab,which is often attributed to variations in material thickness or interface quality without a detailed exploration.Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory.Here,we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions.For the first time,the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated.Moreover,controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated.The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.
基金supported by the National Key Research and Development Program of China(No.2022YFA1204100)the National Natural Science Foundation of China(No.62488201)+1 种基金CAS Project for Young Scientists in Basic Research(No.YSBR-003)the Innovation Program of Quantum Science and Technology(No.2021ZD0302700).
文摘With the explosive expansion of information,there is a growing need for non-volatile memories with high storage density and reconfigurability.Emerging two-dimensional(2D)ferroelectric materials enable the design of various high-performance functional devices that can potentially address these challenges.Here,we report a ferroelectric semiconductor floating-gate transistor based on an α-In_(2)Se_(3)/hexagonal boron nitride(h-BN)/multi-layered graphene(MLG)van der Waals heterostructure on a SiO_(2)/Si substrate.Thanks to the coexistence of both out-of-plane and in-plane polarizations in an α-In_(2)Se_(3) channel,pairs of polarization-modulated channel resistance states can be successfully generated between the floating-gate-modulated on and off states,which can be programmed by either vertical gate pulses or planar drain pulses.These features enable a 2-bit multi-level memory in both three-terminal or two-terminal operational modes,significantly increasing the storage density and reconfigurability.The present results introduce a new design degree of freedom for floating-gate memories and provide fresh insights into future non-volatile memory technologies.
