An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generatio...An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.展开更多
Outdated testing methods hinder the success rate of carbonized cable preparation in low-voltage arc fault tests,leading to incomplete tests and high failure rates.To address this issue,we finely categorized the prepar...Outdated testing methods hinder the success rate of carbonized cable preparation in low-voltage arc fault tests,leading to incomplete tests and high failure rates.To address this issue,we finely categorized the preparation results of carbonized cable specimens by analyzing the experimental phenomena during the carbonization process and assessing the impact of high-voltage energization time on the outcomes,presenting a process control strategy aimed at optimizing the preparation results of carbonized cable specimens.This method utilizes three periodic moving algorithms(root-mean-square,average,and shoulder percentage)to classify the cable specimens into four preparation categories:open-circuit carbonization,under-carbonization,short-circuit carbonization,and successful carbonization.The high-voltage energization time during carbonization or secondary carbonization was adjusted to optimize the preparation of the carbonized cables by considering different discrimination outcomes.Finally,the proposed method was tested on a purpose-built carbonized cable experimental platform,which confirmed its effectiveness in differentiating the preparation outcomes of the carbonized cable specimens and improving the success rate of the carbonized cable preparation.The proposed method has significant potential for application in low-voltage arc fault test systems.展开更多
In recent decades,many software reliability growth models（SRGMs） have been proposed for the engineers and testers in measuring the software reliability precisely.Most of them is established based on the non-homogene...In recent decades,many software reliability growth models（SRGMs） have been proposed for the engineers and testers in measuring the software reliability precisely.Most of them is established based on the non-homogeneous Poisson process（NHPP）,and it is proved that the prediction accuracy of such models could be improved by adding the describing of characterization of testing effort.However,some research work indicates that the fault detection rate（FDR） is another key factor affects final software quality.Most early NHPPbased models deal with the FDR as constant or piecewise function,which does not fit the different testing stages well.Thus,this paper first incorporates a multivariate function of FDR,which is bathtub-shaped,into the NHPP-based SRGMs considering testing effort in order to further improve performance.A new model framework is proposed,and a stepwise method is used to apply the framework with real data sets to find the optimal model.Experimental studies show that the obtained new model can provide better performance of fitting and prediction compared with other traditional SRGMs.展开更多
Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach fo...Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach for virtual testability demonstration test based on stochastic process theory is proposed.First,the similarities and differences of fault sample generation between physical testability demonstration test and virtual testability demonstration test are discussed.Second,it is pointed out that the fault occurrence process subject to perfect repair is renewal process.Third,the interarrival time distribution function of the next fault event is given.Steps and flowcharts of fault sample generation are introduced.The number of faults and their occurrence time are obtained by statistical simulation.Finally,experiments are carried out on a stable tracking platform.Because a variety of types of life distributions and maintenance modes are considered and some assumptions are removed,the sample size and structure of fault sample simulation results are more similar to the actual results and more reasonable.The proposed method can effectively guide the fault injection in virtual testability demonstration test.展开更多
The complex systems are often in the structure of multi-operating modes, and the components implementing system functions are different under different operation modes, which results in the problems that components of...The complex systems are often in the structure of multi-operating modes, and the components implementing system functions are different under different operation modes, which results in the problems that components often fail in different operating modes, faults can be only detected in specified operating modes, tests can be available in specified operating modes,and the cost and efficiency of detecting and isolating faults are different under different operating modes and isolation levels. Aiming at these problems, an optimal test selection method for fault detection and isolation in the multi-operating mode system is proposed by using the fault pair coding and rollout algorithm. Firstly,the faults in fault-test correlation matrices under different operating modes are combined to fault-pairs, which is used to construct the fault pair-test correlation matrices under different operating modes.Secondly, the final fault pair-test correlation matrix of the multioperating mode system is obtained by operating the fault pair-test correlation matrices under different operating modes. Based on the final fault pair-test correlation matrix, the necessary tests are selected by the rollout algorithm orderly. Finally, the effectiveness of the proposed method is verified by examples of the optimal test selection in the multi-operating mode system with faults isolated to different levels. The result shows that the proposed method can effectively mine the fault detection and isolation ability of tests and it is suitable for the optimal test selection of the multi-operating mode system with faults isolated to the replacement unit and specific fault.展开更多
This paper deals with the target-fault-oriented test generation of sequential circuits using genetic algorithms. We adopted the concept of multiple phases and proposed four sub-procedures which consist of activation, ...This paper deals with the target-fault-oriented test generation of sequential circuits using genetic algorithms. We adopted the concept of multiple phases and proposed four sub-procedures which consist of activation, propagation and justification phases. The paper focuses on the design of genetic operators and construction of fitness functions which are based on the structure information of circuits. Using ISCAS89 benchmarks, the experiment results of GA were given.展开更多
In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presente...In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the advantages of the proposed testing scheme.展开更多
A new online system of monitoring yarn quality and fault diagnosis is presented. This system integrates the technologies of sensor, signal process, communication, network, computer, control, instrument structure and m...A new online system of monitoring yarn quality and fault diagnosis is presented. This system integrates the technologies of sensor, signal process, communication, network, computer, control, instrument structure and mass knowledge of experts. Comparing with conventional off-line yarn test, the new system can find the quality defects of yarn online in time and compensate for the lack of expert knowledge in manual analysis. It can save a lot of yarn wasted in off-line test and improve product quality. By using laser sensor to sample the diameter signal of yarn and doing wavelet analysis and FFT to extract fault characteristics, a set of reasoning mechanism is established to analyze yarn quality and locate the fault origination. The experimental results show that new system can do well in monitoring yarn quality online comparing with conventional off-line yarn test. It can test the quality of yarn in real-time with high efficiency and analyze the fault reason accurately. It is very useful to apply this new system to upgrade yarn quality in cotton textile industry at present.展开更多
Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the numbe...Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.展开更多
Test points selection for integer-coded fault wise table is a discrete optimization problem. On one hand, traditional exhaustive search method is computationally expensive. On the other hand, the space complexity of t...Test points selection for integer-coded fault wise table is a discrete optimization problem. On one hand, traditional exhaustive search method is computationally expensive. On the other hand, the space complexity of traditional exhaustive is low. A tradeoff method between the high time complexity and low space complexity is proposed. At first, a new fault-pair table is constructed based on the integer-coded fault wise table. The fault-pair table consists of two columns： one column represents fault pair and the other represents test points set that can distinguish the corresponding faults. Then, the rows are arranged in ascending order according to the cardinality of corresponding test points set. Thirdly, test points in the top rows are selected one by one until all fault pair are isolated. During the test points selection process, the rows that contain selected test points are deleted and then the dimension of fault-pair table decreases gradually. The proposed test points selection algorithm is illustrated and tested using an integercoded fault wise table derived from a real analog circuit. Computational results suggest show policies are better than the exhaustive strategy.展开更多
In order to improve the accuracy of cable fault position location at a low cost and make the testing results intuitive, a cable fault detector based on wave form reconstruction is designed. In this detector, the cable...In order to improve the accuracy of cable fault position location at a low cost and make the testing results intuitive, a cable fault detector based on wave form reconstruction is designed. In this detector, the cable fault position is located based on the time-domain pulse reflection （TDR） principle. A pulse waveform is injected in the tested cable, and a high-speed comparator with changeable reference voltages is used to binarize the test pulse waveform to a binary sequence on a certain voltage. Through scanning the reference voltage in a full voltage range, multi-sequences are acquired to reconstruct the pulse waveform transmission in the cable, and then the pulse attenuation feature, electrical open circuit fault, electrical short circuit fault, and the fault position of the cable are diagnosed. Experimental results show that the designed cable fault detector can determine the fault type and its position of the cable being tested, and the testing results are intuitive.展开更多
In order to optimize test flow after the default flow is modified by a tester, a new software framework for the radar fault isolation is illustrated. This framework separates all mapping algorithms from test flows so ...In order to optimize test flow after the default flow is modified by a tester, a new software framework for the radar fault isolation is illustrated. This framework separates all mapping algorithms from test flows so as to modify flow and to insert mapping algorithm dynamically in testing process. Based on this framework, a kind of optimization method of test flow is proposed and studied. By defining an objective function, we can evaluate all candidate test flows so as to get an optimized flow. An example explains how to search the flow from candidate flows.展开更多
In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant...In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..展开更多
Test points selection for integer-coded fault wise table is a discrete optimization problem. The global minimum set of test points can only be guaranteed by an exhaustive search which is eompurationally expensive. In ...Test points selection for integer-coded fault wise table is a discrete optimization problem. The global minimum set of test points can only be guaranteed by an exhaustive search which is eompurationally expensive. In this paper, this problem is formulated as a heuristic depth-first graph search problem at first. The graph node expanding method and rules are given. Then, rollout strategies are applied, which can be combined with the heuristic graph search algorithms, in a computationally more efficient manner than the optimal strategies, to obtain solutions superior to those using the greedy heuristic algorithms. The proposed rollout-based test points selection algorithm is illustrated and tested using an analog circuit and a set of simulated integer-coded fault wise tables. Computa- tional results are shown, which suggest that the rollout strategy policies are significantly better than other strategies.展开更多
This investigation deals with the intelligent system for parallel fault-tolerant diagnostic tests construction. A modified parallel algorithm for fault-tolerant diagnostic tests construction is proposed. The algorithm...This investigation deals with the intelligent system for parallel fault-tolerant diagnostic tests construction. A modified parallel algorithm for fault-tolerant diagnostic tests construction is proposed. The algorithm is allowed to optimize processing time on tests construction. A matrix model of data and knowledge representation, as well as various kinds of regularities in data and knowledge are presented. Applied intelligent system for diagnostic of mental health of population which is developed with the use of intelligent system for parallel fault-tolerant DTs construction is suggested.展开更多
Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or ...Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.展开更多
Results of analysis of variation of cross fault short-baseline and short-range leveling in Western Yunnan Earthquake Test Site (WYETS), results show that among five observation stations of cross fault short-baseline a...Results of analysis of variation of cross fault short-baseline and short-range leveling in Western Yunnan Earthquake Test Site (WYETS), results show that among five observation stations of cross fault short-baseline and short-range leveling in WYETS before the Lijiang MS7.0 Earthquake occurred in February 1996 only Yongsheng observation station (epicentral distance 82 km) located at Chenghai fault shows great variation about one year before the earthquake. And the nearest observation station, Lijiang (epicentral distance 42 km); presents great coseismic variation, but does not show obvious anomalous variation before the earthquake. There are no significant variations related to the earthquake at the other three observation stations. Two methods are used in analysis of the observed data and some valuable results have been obtained.展开更多
基金This project was supported by the National Natural Science Foundation of China (90407007).
文摘An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.
基金Supported by the National Natural Science Foundation of China(52277136)the University Production-Study Cooperation Project of Science and Technology Department of Fujian Province(2021Y4002)+1 种基金the 2018 Funding Program for Leading Talents in Scientific and Technological Innovation of Fujian(038000387024)Natural Science Foundation of Fujian Province(2020J05170).
文摘Outdated testing methods hinder the success rate of carbonized cable preparation in low-voltage arc fault tests,leading to incomplete tests and high failure rates.To address this issue,we finely categorized the preparation results of carbonized cable specimens by analyzing the experimental phenomena during the carbonization process and assessing the impact of high-voltage energization time on the outcomes,presenting a process control strategy aimed at optimizing the preparation results of carbonized cable specimens.This method utilizes three periodic moving algorithms(root-mean-square,average,and shoulder percentage)to classify the cable specimens into four preparation categories:open-circuit carbonization,under-carbonization,short-circuit carbonization,and successful carbonization.The high-voltage energization time during carbonization or secondary carbonization was adjusted to optimize the preparation of the carbonized cables by considering different discrimination outcomes.Finally,the proposed method was tested on a purpose-built carbonized cable experimental platform,which confirmed its effectiveness in differentiating the preparation outcomes of the carbonized cable specimens and improving the success rate of the carbonized cable preparation.The proposed method has significant potential for application in low-voltage arc fault test systems.
基金supported by the National Natural Science Foundation of China(61070220)the Anhui Provincial Natural Science Foundation(1408085MKL79)
文摘In recent decades,many software reliability growth models（SRGMs） have been proposed for the engineers and testers in measuring the software reliability precisely.Most of them is established based on the non-homogeneous Poisson process（NHPP）,and it is proved that the prediction accuracy of such models could be improved by adding the describing of characterization of testing effort.However,some research work indicates that the fault detection rate（FDR） is another key factor affects final software quality.Most early NHPPbased models deal with the FDR as constant or piecewise function,which does not fit the different testing stages well.Thus,this paper first incorporates a multivariate function of FDR,which is bathtub-shaped,into the NHPP-based SRGMs considering testing effort in order to further improve performance.A new model framework is proposed,and a stepwise method is used to apply the framework with real data sets to find the optimal model.Experimental studies show that the obtained new model can provide better performance of fitting and prediction compared with other traditional SRGMs.
基金National Natural Science Foundation of China(51105369)
文摘Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach for virtual testability demonstration test based on stochastic process theory is proposed.First,the similarities and differences of fault sample generation between physical testability demonstration test and virtual testability demonstration test are discussed.Second,it is pointed out that the fault occurrence process subject to perfect repair is renewal process.Third,the interarrival time distribution function of the next fault event is given.Steps and flowcharts of fault sample generation are introduced.The number of faults and their occurrence time are obtained by statistical simulation.Finally,experiments are carried out on a stable tracking platform.Because a variety of types of life distributions and maintenance modes are considered and some assumptions are removed,the sample size and structure of fault sample simulation results are more similar to the actual results and more reasonable.The proposed method can effectively guide the fault injection in virtual testability demonstration test.
基金supported by the Natural Science Foundation of Shannxi Province(2017JQ5016)the Joint Laboratory for Sea Measurement and Control of Aircraft(DOM2016OF011)
文摘The complex systems are often in the structure of multi-operating modes, and the components implementing system functions are different under different operation modes, which results in the problems that components often fail in different operating modes, faults can be only detected in specified operating modes, tests can be available in specified operating modes,and the cost and efficiency of detecting and isolating faults are different under different operating modes and isolation levels. Aiming at these problems, an optimal test selection method for fault detection and isolation in the multi-operating mode system is proposed by using the fault pair coding and rollout algorithm. Firstly,the faults in fault-test correlation matrices under different operating modes are combined to fault-pairs, which is used to construct the fault pair-test correlation matrices under different operating modes.Secondly, the final fault pair-test correlation matrix of the multioperating mode system is obtained by operating the fault pair-test correlation matrices under different operating modes. Based on the final fault pair-test correlation matrix, the necessary tests are selected by the rollout algorithm orderly. Finally, the effectiveness of the proposed method is verified by examples of the optimal test selection in the multi-operating mode system with faults isolated to different levels. The result shows that the proposed method can effectively mine the fault detection and isolation ability of tests and it is suitable for the optimal test selection of the multi-operating mode system with faults isolated to the replacement unit and specific fault.
文摘This paper deals with the target-fault-oriented test generation of sequential circuits using genetic algorithms. We adopted the concept of multiple phases and proposed four sub-procedures which consist of activation, propagation and justification phases. The paper focuses on the design of genetic operators and construction of fitness functions which are based on the structure information of circuits. Using ISCAS89 benchmarks, the experiment results of GA were given.
文摘In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the advantages of the proposed testing scheme.
文摘A new online system of monitoring yarn quality and fault diagnosis is presented. This system integrates the technologies of sensor, signal process, communication, network, computer, control, instrument structure and mass knowledge of experts. Comparing with conventional off-line yarn test, the new system can find the quality defects of yarn online in time and compensate for the lack of expert knowledge in manual analysis. It can save a lot of yarn wasted in off-line test and improve product quality. By using laser sensor to sample the diameter signal of yarn and doing wavelet analysis and FFT to extract fault characteristics, a set of reasoning mechanism is established to analyze yarn quality and locate the fault origination. The experimental results show that new system can do well in monitoring yarn quality online comparing with conventional off-line yarn test. It can test the quality of yarn in real-time with high efficiency and analyze the fault reason accurately. It is very useful to apply this new system to upgrade yarn quality in cotton textile industry at present.
文摘Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.
基金supported by National Natural Science Foundation of China under Grant No.60934002General Armament Department under Grant No.51317040102
文摘Test points selection for integer-coded fault wise table is a discrete optimization problem. On one hand, traditional exhaustive search method is computationally expensive. On the other hand, the space complexity of traditional exhaustive is low. A tradeoff method between the high time complexity and low space complexity is proposed. At first, a new fault-pair table is constructed based on the integer-coded fault wise table. The fault-pair table consists of two columns： one column represents fault pair and the other represents test points set that can distinguish the corresponding faults. Then, the rows are arranged in ascending order according to the cardinality of corresponding test points set. Thirdly, test points in the top rows are selected one by one until all fault pair are isolated. During the test points selection process, the rows that contain selected test points are deleted and then the dimension of fault-pair table decreases gradually. The proposed test points selection algorithm is illustrated and tested using an integercoded fault wise table derived from a real analog circuit. Computational results suggest show policies are better than the exhaustive strategy.
基金The National Natural Science Foundation of China(No.61240032)the Natural Science Foundation of Jiangsu Province(No.BK2012560)+1 种基金the College Scientific and Technological Achievements Transformation Promotion Project of Jiangsu Province(No.JH-05)the Science and Technology Support Program of Jiangsu Province(No.BE2012740)
文摘In order to improve the accuracy of cable fault position location at a low cost and make the testing results intuitive, a cable fault detector based on wave form reconstruction is designed. In this detector, the cable fault position is located based on the time-domain pulse reflection （TDR） principle. A pulse waveform is injected in the tested cable, and a high-speed comparator with changeable reference voltages is used to binarize the test pulse waveform to a binary sequence on a certain voltage. Through scanning the reference voltage in a full voltage range, multi-sequences are acquired to reconstruct the pulse waveform transmission in the cable, and then the pulse attenuation feature, electrical open circuit fault, electrical short circuit fault, and the fault position of the cable are diagnosed. Experimental results show that the designed cable fault detector can determine the fault type and its position of the cable being tested, and the testing results are intuitive.
文摘In order to optimize test flow after the default flow is modified by a tester, a new software framework for the radar fault isolation is illustrated. This framework separates all mapping algorithms from test flows so as to modify flow and to insert mapping algorithm dynamically in testing process. Based on this framework, a kind of optimization method of test flow is proposed and studied. By defining an objective function, we can evaluate all candidate test flows so as to get an optimized flow. An example explains how to search the flow from candidate flows.
文摘In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..
基金supported by Commission of Science Technology and Industry for National Defence of China under Grant No.A1420061264National Natural Science Foundation of China under Grant No.60934002General Armament Department under Grand No.51317040102)
文摘Test points selection for integer-coded fault wise table is a discrete optimization problem. The global minimum set of test points can only be guaranteed by an exhaustive search which is eompurationally expensive. In this paper, this problem is formulated as a heuristic depth-first graph search problem at first. The graph node expanding method and rules are given. Then, rollout strategies are applied, which can be combined with the heuristic graph search algorithms, in a computationally more efficient manner than the optimal strategies, to obtain solutions superior to those using the greedy heuristic algorithms. The proposed rollout-based test points selection algorithm is illustrated and tested using an analog circuit and a set of simulated integer-coded fault wise tables. Computa- tional results are shown, which suggest that the rollout strategy policies are significantly better than other strategies.
文摘This investigation deals with the intelligent system for parallel fault-tolerant diagnostic tests construction. A modified parallel algorithm for fault-tolerant diagnostic tests construction is proposed. The algorithm is allowed to optimize processing time on tests construction. A matrix model of data and knowledge representation, as well as various kinds of regularities in data and knowledge are presented. Applied intelligent system for diagnostic of mental health of population which is developed with the use of intelligent system for parallel fault-tolerant DTs construction is suggested.
文摘Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.
基金This project was sponsored by the Application Basis Research Foundation of Yunnan Province (97D06), China.
文摘Results of analysis of variation of cross fault short-baseline and short-range leveling in Western Yunnan Earthquake Test Site (WYETS), results show that among five observation stations of cross fault short-baseline and short-range leveling in WYETS before the Lijiang MS7.0 Earthquake occurred in February 1996 only Yongsheng observation station (epicentral distance 82 km) located at Chenghai fault shows great variation about one year before the earthquake. And the nearest observation station, Lijiang (epicentral distance 42 km); presents great coseismic variation, but does not show obvious anomalous variation before the earthquake. There are no significant variations related to the earthquake at the other three observation stations. Two methods are used in analysis of the observed data and some valuable results have been obtained.
