Structured flowchart( SFC) and Automatic code generation based on SFC( CG-SFC) have been widely used in software requirements,design and testing phases. Some CG-SFC tools such as Rhapsody have the ability to build flo...Structured flowchart( SFC) and Automatic code generation based on SFC( CG-SFC) have been widely used in software requirements,design and testing phases. Some CG-SFC tools such as Rhapsody have the ability to build flowchart and generate code,but they do not check whether a given flowchart is correct or structural. For unstructured error ‘goto'statements will be generated randomly. We proposed three algorithms and some error recognition criteria to solve those problems. Structure recognition algorithm can recognize Selection,While/for and do-while structures. Error recognition algorithm incorporating criteria can check all the errors. At last,we develop a CG-SFC system,and compared with existing Rhapsody,it shows that the proposed algorithms are correct and effective.展开更多
This paper proposes a generic high-performance and low-time-overhead software control flow checking solution, graph-tree-based control flow checking （GTCFC） for space-borne commercial-off-the-shelf （COTS） processo...This paper proposes a generic high-performance and low-time-overhead software control flow checking solution, graph-tree-based control flow checking （GTCFC） for space-borne commercial-off-the-shelf （COTS） processors. A graph tree data structure with a topology similar to common trees is introduced to transform the control flow graphs of target programs. This together with design of IDs and signatures of its vertices and edges allows for an easy check of legality of actual branching during target program execution. As a result, the algorithm not only is capable of detecting all single and multiple branching errors with low latency and time overheads along with a linear-complexity space overhead, but also remains generic among arbitrary instruction sets and independent of any specific hardware. Tests of the algorithm using a COTS-processor-based onboard computer （OBC） of in-service ZDPS-1A pico-satellite products show that GTCFC can detect over 90% of the randomly injected and all-pattern-covering branching errors for different types of target programs, with performance and overheads consistent with the theoretical analysis; and beats well-established preeminent control flow checking algorithms in these dimensions. Furthermore, it is validated that GTCGC not only can be accommodated in pico-satellites conveniently with still sufficient system margins left, but also has the ability to minimize the risk of control flow errors being undetected in their space missions. Therefore, due to its effectiveness, efficiency, and compatibility, the GTCFC solution is ready for applications on COTS processors on pico-satellites in their real space missions.展开更多
CAD model with nominal dimension is implemented in interference checking of assembly simulation of aircraft complex parts at present, which causes inadequate availability. In order to address this challenging issue, i...CAD model with nominal dimension is implemented in interference checking of assembly simulation of aircraft complex parts at present, which causes inadequate availability. In order to address this challenging issue, interference checking method with tolerance based on assembly dimension chain was proposed. Worst case and maximum error probability of tolerance of composing loop were used, and CAD models were respectively re-constructed and inserted into simulation system. Before dynamic interference checking, engineering semantic interference condition was set to assembly requirements. Finally, the interface checking result was a basis for reasonability of assembly process and tolerance. A prototype system was developed based on the above research.展开更多
Abstract Single event upset （SEU） effect, caused by highly energized particles in aerospace, threatens the reliability and security of small satellites composed of commercialofftheshelves （COTS）. SEU induced contr...Abstract Single event upset （SEU） effect, caused by highly energized particles in aerospace, threatens the reliability and security of small satellites composed of commercialofftheshelves （COTS）. SEU induced control flow errors （CFEs） may cause unpredictable behavior or crashes of COTSbased small satellites. This paper proposes a generic softwarebased control flow checking technique （CFC） and bipartite graphbased control flow checking （BGCFC）. To simplify the types of illegal branches, it transforms the conventional control flow graph into the equivalent bipartite graph. It checks the legal ity of control flow at runtime by comparing a global signature with the expected value and introduces consecutive IDs and bitmaps to reduce the time and memory overhead. Theoretical analysis shows that BGCFC can detect all types of internode CFEs with constant time and memory overhead. Practical tests verify the result of theoretical analysis. Compared with previous techniques, BGCFC achieves the highest error detection rate, lower time and memory overhead; the composite result in evaluation fac tor shows that BGCFC is the most effective one among all these techniques. The results in both theory and practice verify the applicability of BGCFC for COTSbased small satellites.展开更多
QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easil...QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on ＂half-change＂ Gray coding are researched. Because of the probable error impact of QLC NAND cell＇s voltage change, the solution of generating the soft information after XOR（exclusive OR） the soft bits by internal read mechanism is presented for Low-Density Parity-Check（LDPC） Belief Propagation（BP） decoding in QLC design for its system level application.展开更多
针对目前行人航位推算(pedestrian dead reckoning,PDR)定位过程中存在累积误差,导致PDR定位轨迹存在较大偏移的问题,提出了一种基于闭合差校正的PDR定位轨迹优化方法,该方法利用PDR轨迹的闭合差对每一步的定位结果进行校正,从而整体优...针对目前行人航位推算(pedestrian dead reckoning,PDR)定位过程中存在累积误差,导致PDR定位轨迹存在较大偏移的问题,提出了一种基于闭合差校正的PDR定位轨迹优化方法,该方法利用PDR轨迹的闭合差对每一步的定位结果进行校正,从而整体优化PDR定位的轨迹,提高定位精度.实验结果表明,基于闭合差校正的PDR定位轨迹整体上更接近实际轨迹,校正后的PDR平均定位误差减少0.283 4 m,在1 m以内的累积误差概率相较于校正之前提高了22%,有效提高了PDR定位精度,定位轨迹得到进一步优化.展开更多
基金Sponsored by the National Natural Science Foundation of China(Grant No.61402131)the China Postdoctoral Science Foundation(Grant No.2014M551245,2016T90293)+1 种基金the Heilongjiang Postdoctoral Science Foundation(Grant No.LBH-Z13105)the Fundamental Research Funds for the Central Universities(Grant No.HIT.NSRIF.201651)
文摘Structured flowchart( SFC) and Automatic code generation based on SFC( CG-SFC) have been widely used in software requirements,design and testing phases. Some CG-SFC tools such as Rhapsody have the ability to build flowchart and generate code,but they do not check whether a given flowchart is correct or structural. For unstructured error ‘goto'statements will be generated randomly. We proposed three algorithms and some error recognition criteria to solve those problems. Structure recognition algorithm can recognize Selection,While/for and do-while structures. Error recognition algorithm incorporating criteria can check all the errors. At last,we develop a CG-SFC system,and compared with existing Rhapsody,it shows that the proposed algorithms are correct and effective.
基金supported by National Natural Science Foundation of China (No. 60904090)
文摘This paper proposes a generic high-performance and low-time-overhead software control flow checking solution, graph-tree-based control flow checking （GTCFC） for space-borne commercial-off-the-shelf （COTS） processors. A graph tree data structure with a topology similar to common trees is introduced to transform the control flow graphs of target programs. This together with design of IDs and signatures of its vertices and edges allows for an easy check of legality of actual branching during target program execution. As a result, the algorithm not only is capable of detecting all single and multiple branching errors with low latency and time overheads along with a linear-complexity space overhead, but also remains generic among arbitrary instruction sets and independent of any specific hardware. Tests of the algorithm using a COTS-processor-based onboard computer （OBC） of in-service ZDPS-1A pico-satellite products show that GTCFC can detect over 90% of the randomly injected and all-pattern-covering branching errors for different types of target programs, with performance and overheads consistent with the theoretical analysis; and beats well-established preeminent control flow checking algorithms in these dimensions. Furthermore, it is validated that GTCGC not only can be accommodated in pico-satellites conveniently with still sufficient system margins left, but also has the ability to minimize the risk of control flow errors being undetected in their space missions. Therefore, due to its effectiveness, efficiency, and compatibility, the GTCFC solution is ready for applications on COTS processors on pico-satellites in their real space missions.
基金Supported by the National Natural Science Foundation Project of China (No.50905087)the National Science and Technology Major Project of China (2012ZX04010041)the Aeronautical Science Foundation Project of China (2010ZE52057)
文摘CAD model with nominal dimension is implemented in interference checking of assembly simulation of aircraft complex parts at present, which causes inadequate availability. In order to address this challenging issue, interference checking method with tolerance based on assembly dimension chain was proposed. Worst case and maximum error probability of tolerance of composing loop were used, and CAD models were respectively re-constructed and inserted into simulation system. Before dynamic interference checking, engineering semantic interference condition was set to assembly requirements. Finally, the interface checking result was a basis for reasonability of assembly process and tolerance. A prototype system was developed based on the above research.
基金support from the National Natural Science Foundation of Chinathe Fundamental Research Funds for the Central Universities of China
文摘Abstract Single event upset （SEU） effect, caused by highly energized particles in aerospace, threatens the reliability and security of small satellites composed of commercialofftheshelves （COTS）. SEU induced control flow errors （CFEs） may cause unpredictable behavior or crashes of COTSbased small satellites. This paper proposes a generic softwarebased control flow checking technique （CFC） and bipartite graphbased control flow checking （BGCFC）. To simplify the types of illegal branches, it transforms the conventional control flow graph into the equivalent bipartite graph. It checks the legal ity of control flow at runtime by comparing a global signature with the expected value and introduces consecutive IDs and bitmaps to reduce the time and memory overhead. Theoretical analysis shows that BGCFC can detect all types of internode CFEs with constant time and memory overhead. Practical tests verify the result of theoretical analysis. Compared with previous techniques, BGCFC achieves the highest error detection rate, lower time and memory overhead; the composite result in evaluation fac tor shows that BGCFC is the most effective one among all these techniques. The results in both theory and practice verify the applicability of BGCFC for COTSbased small satellites.
文摘QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on ＂half-change＂ Gray coding are researched. Because of the probable error impact of QLC NAND cell＇s voltage change, the solution of generating the soft information after XOR（exclusive OR） the soft bits by internal read mechanism is presented for Low-Density Parity-Check（LDPC） Belief Propagation（BP） decoding in QLC design for its system level application.
