In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline ar...In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.展开更多
文摘In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.
