Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environ...Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.展开更多
Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi...Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems.展开更多
A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） mult...A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.展开更多
The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transisto...The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.展开更多
A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not ...A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.展开更多
Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in cu...Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.展开更多
A 7-chip, 280 Gb/s optical code-division multiplexing （OCDM） system incorporating quaternary phase coding and decoding superstructured fiber Bragg gratings （SSFBGs） is experimentally demonstrated. Only ordinary ph...A 7-chip, 280 Gb/s optical code-division multiplexing （OCDM） system incorporating quaternary phase coding and decoding superstructured fiber Bragg gratings （SSFBGs） is experimentally demonstrated. Only ordinary phase masks and sub-micrometer precision are needed to fabricate the encoding and decoding SSFBGs. Interchannel interference noise is also considered and evaluated, 2-channel 40 （Gb/s）/channel （2 ×40 Gb/s） signal transmission is demonstrated.展开更多
Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of...Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.展开更多
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU)and the variable node unit(VNU)based on min-sum(MS)algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT)is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fix...An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fixed initial radius, the ILSD adopts an adaptive radius to accelerate the list cdnstruction. Characterized by low-complexity and radius-insensitivity, the proposed algorithm makes iterative joint detection and decoding more realizable in multiple-antenna systems. Simulation results show that computational savings of ILSD over LSD are more apparent with more transmit antennas or larger constellations, and with no performance degradation. Because the complexity of the ILSD algorithm almost keeps invariant with the increasing of initial radius, the BER performance can be improved by selecting a sufficiently large radius.展开更多
A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces...A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.展开更多
On an internet of video things(IoVT), an encoder needs to collect a large number of signal samples to improve the reconstruction quality. It is challenging to some occasions where the resources of an encoder are extre...On an internet of video things(IoVT), an encoder needs to collect a large number of signal samples to improve the reconstruction quality. It is challenging to some occasions where the resources of an encoder are extremely limited. The distributed video compressive sensing(DVCS) can save a lot of resources for the encoder. For the skip-block coding at such an encoder, this paper proposes a motion-adaptive adjacent-reference skipping(MAS) algorithm for DVCS with general decoders. The proposed algorithm makes full use of the spatial-temporal correlation between consecutive frames, and the reconstruction quality can be improved significantly. What’s more, the skipping ratio of non-keyframes is adaptive to the difference of their motion-speeds. The proposed algorithm does not need to change any decoder, so it can be easily applied to general decoders. The simulation results show that under different skipping ratios, the proposed algorithm can achieve better reconstruction quality than other existing algorithms, and thus improve the energy-efficiency of the encoder.展开更多
基金supported by the National Natural Science Foundation of China under Grant No.62001440。
文摘Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.
基金supported in part by the National Natural Science Foundation of China under Grant 6226070954Jiangxi Provincial Key R&D Programme under Grant 20244BBG73002.
文摘Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems.
文摘A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.
文摘The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.
基金The National Natural Science Foundation of China(No.60871079)
文摘A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.
基金Project supported by the Natural Science Foundation of Shandong Province,China(Grant No.ZR2021MF049)Joint Fund of Natural Science Foundation of Shandong Province(Grant Nos.ZR2022LLZ012 and ZR2021LLZ001)the Key R&D Program of Shandong Province,China(Grant No.2023CXGC010901)。
文摘Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.
基金This work was supported by the state "863" High Technology Program of China under Grant No. 2002AA122035.
文摘A 7-chip, 280 Gb/s optical code-division multiplexing （OCDM） system incorporating quaternary phase coding and decoding superstructured fiber Bragg gratings （SSFBGs） is experimentally demonstrated. Only ordinary phase masks and sub-micrometer precision are needed to fabricate the encoding and decoding SSFBGs. Interchannel interference noise is also considered and evaluated, 2-channel 40 （Gb/s）/channel （2 ×40 Gb/s） signal transmission is demonstrated.
基金supported in part by National Nature Science Foundation of China under Grant No.61471286,No.61271004the Fundamental Research Funds for the Central Universitiesthe open research fund of Key Laboratory of Information Coding and Transmission,Southwest Jiaotong University(No.2010-03)
文摘Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU)and the variable node unit(VNU)based on min-sum(MS)algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT)is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
基金The National Natural Science Founda-tion of China ( No 60496316)the National Hi-Tech Re-search and Development Program (863) of China (No2006-AA01Z270)
文摘An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fixed initial radius, the ILSD adopts an adaptive radius to accelerate the list cdnstruction. Characterized by low-complexity and radius-insensitivity, the proposed algorithm makes iterative joint detection and decoding more realizable in multiple-antenna systems. Simulation results show that computational savings of ILSD over LSD are more apparent with more transmit antennas or larger constellations, and with no performance degradation. Because the complexity of the ILSD algorithm almost keeps invariant with the increasing of initial radius, the BER performance can be improved by selecting a sufficiently large radius.
文摘A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.
基金supported by the National Natural Science Foundation of China(No.62001099)。
文摘On an internet of video things(IoVT), an encoder needs to collect a large number of signal samples to improve the reconstruction quality. It is challenging to some occasions where the resources of an encoder are extremely limited. The distributed video compressive sensing(DVCS) can save a lot of resources for the encoder. For the skip-block coding at such an encoder, this paper proposes a motion-adaptive adjacent-reference skipping(MAS) algorithm for DVCS with general decoders. The proposed algorithm makes full use of the spatial-temporal correlation between consecutive frames, and the reconstruction quality can be improved significantly. What’s more, the skipping ratio of non-keyframes is adaptive to the difference of their motion-speeds. The proposed algorithm does not need to change any decoder, so it can be easily applied to general decoders. The simulation results show that under different skipping ratios, the proposed algorithm can achieve better reconstruction quality than other existing algorithms, and thus improve the energy-efficiency of the encoder.
