This paper presents a dual voltage-controlled-delay-line（VCDL） delay-lock-loop（DLL） based gate driver for a zero-voltage-switching（ZVS） DC-DC converter.Using the delay difference of two VCDLs for the dead time c...This paper presents a dual voltage-controlled-delay-line（VCDL） delay-lock-loop（DLL） based gate driver for a zero-voltage-switching（ZVS） DC-DC converter.Using the delay difference of two VCDLs for the dead time control,the dual VCDL DLL is able to implement ZVS control with high accuracy while keeping good linearity performance of the DLL and low power consumption.The design is implemented in the CSM 2P4M 0.35μm CMOS process.The measurement results indicate that an efficiency improvement of 2%-4%is achieved over the load current range from 100 to 600 mA at 4 MHz switching frequency with 3.3 V input and 1.3 V output voltage.展开更多
基金Project supported by the National Natural Science Foundation of China(No.60676013).
文摘This paper presents a dual voltage-controlled-delay-line（VCDL） delay-lock-loop（DLL） based gate driver for a zero-voltage-switching（ZVS） DC-DC converter.Using the delay difference of two VCDLs for the dead time control,the dual VCDL DLL is able to implement ZVS control with high accuracy while keeping good linearity performance of the DLL and low power consumption.The design is implemented in the CSM 2P4M 0.35μm CMOS process.The measurement results indicate that an efficiency improvement of 2%-4%is achieved over the load current range from 100 to 600 mA at 4 MHz switching frequency with 3.3 V input and 1.3 V output voltage.
