BACKGROUND： Enhanced recovery after surgery（ERAS） has improved postoperative outcomes particularly in colorectal surgery. This study aimed to assess compliance with an ERAS protocol and evaluate its effect on posto...BACKGROUND： Enhanced recovery after surgery（ERAS） has improved postoperative outcomes particularly in colorectal surgery. This study aimed to assess compliance with an ERAS protocol and evaluate its effect on postoperative outcomes in patients undergoing pancreaticoduodenectomy. METHODS： Fifty patients who had received conventional peri operative management from 2005 to 2009（conventional group）were compared with 75 patients who had received perioperative care with an ERAS protocol（fast-track group） from 2010 to2014. Mortality, complications, readmissions and length of hospital stay were evaluated and compared in the groups.RESULTS： Compliance with each element of the ERAS pro tocol ranged from 74.7% to 100%. Uneventful patients had a significant higher adherence to the ERAS protocol（87.5% vs40.7%; P〈0.001）. There were no significant differences in de mographics and perioperative characteristics between the two groups. Patients in the fast-track group had a shorter time to remove the nasogastric tube, start liquid diet and solid food pass flatus and stools, and remove drains. No difference was found in mortality, relaparotomy, readmission rates and over all morbidity. However, delayed gastric emptying and length of hospital stay were significantly reduced in the fast-track group. The independent effect of the ERAS protocol in reduc ing delayed gastric emptying and length of hospital stay was confirmed by multivariate analysis.CONCLUSION： ERAS pathway was feasible and safe in improving gastric emptying, yielding an earlier postoperative recovery, and reducing the length of hospital stay.展开更多
A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many po...A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.展开更多
Existing studies on modern roundabouts performance are mostly based on data fron： singe lane roundabouts that are not heavily congested. For planners and designers interested in building multilane roundabouts for int...Existing studies on modern roundabouts performance are mostly based on data fron： singe lane roundabouts that are not heavily congested. For planners and designers interested in building multilane roundabouts for intersections with potential growth i~ future traffic, there has been a lack of existing studies with field data that provide reference values in terms of capacity and delay measurements. With the intent of providing such reference values, a case study was conducted by using the East DowlinC Road Roundabouts in Anchorage, Alaska, which are currently operating with extensive queues during the evening peak hours. This research used multiple video camcorders t（ capture vehicle turning movements at the roundabouts as well as the progressior~ of vehicle queues at the roundabout entrance approaches. With these video records, the number of vehicles in the queues can be accurately counted in any single minute during the peak hours. This study shows that unbalanced entrance flow patterns （i.e., ~ne entrance has significant higher flow than others） can intensify the queue and delay fo., the overall roundabouts. Then various software packages including RODEL, SIDRA and VISSIM were used to estimate several performance measurements, such as capacity. queue length, and delay, compared with the collected field data. With the comparison, it is found that all the three software packages overestimate multi-lane roundabout ca pacity before calibration. With default parameters, SIDRA and VISSIM tend to underes timate delays and queue lengths for the multi-lane roundabouts under congestion, while RODEL results in higher delay and queue length estimations at most of the entrance approaches.展开更多
文摘BACKGROUND： Enhanced recovery after surgery（ERAS） has improved postoperative outcomes particularly in colorectal surgery. This study aimed to assess compliance with an ERAS protocol and evaluate its effect on postoperative outcomes in patients undergoing pancreaticoduodenectomy. METHODS： Fifty patients who had received conventional peri operative management from 2005 to 2009（conventional group）were compared with 75 patients who had received perioperative care with an ERAS protocol（fast-track group） from 2010 to2014. Mortality, complications, readmissions and length of hospital stay were evaluated and compared in the groups.RESULTS： Compliance with each element of the ERAS pro tocol ranged from 74.7% to 100%. Uneventful patients had a significant higher adherence to the ERAS protocol（87.5% vs40.7%; P〈0.001）. There were no significant differences in de mographics and perioperative characteristics between the two groups. Patients in the fast-track group had a shorter time to remove the nasogastric tube, start liquid diet and solid food pass flatus and stools, and remove drains. No difference was found in mortality, relaparotomy, readmission rates and over all morbidity. However, delayed gastric emptying and length of hospital stay were significantly reduced in the fast-track group. The independent effect of the ERAS protocol in reduc ing delayed gastric emptying and length of hospital stay was confirmed by multivariate analysis.CONCLUSION： ERAS pathway was feasible and safe in improving gastric emptying, yielding an earlier postoperative recovery, and reducing the length of hospital stay.
文摘A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.
基金sponsored by Alaska University Transportation Center(AUTC,No.RR08.08)Alaska Department of Transportation(AK DOT)
文摘Existing studies on modern roundabouts performance are mostly based on data fron： singe lane roundabouts that are not heavily congested. For planners and designers interested in building multilane roundabouts for intersections with potential growth i~ future traffic, there has been a lack of existing studies with field data that provide reference values in terms of capacity and delay measurements. With the intent of providing such reference values, a case study was conducted by using the East DowlinC Road Roundabouts in Anchorage, Alaska, which are currently operating with extensive queues during the evening peak hours. This research used multiple video camcorders t（ capture vehicle turning movements at the roundabouts as well as the progressior~ of vehicle queues at the roundabout entrance approaches. With these video records, the number of vehicles in the queues can be accurately counted in any single minute during the peak hours. This study shows that unbalanced entrance flow patterns （i.e., ~ne entrance has significant higher flow than others） can intensify the queue and delay fo., the overall roundabouts. Then various software packages including RODEL, SIDRA and VISSIM were used to estimate several performance measurements, such as capacity. queue length, and delay, compared with the collected field data. With the comparison, it is found that all the three software packages overestimate multi-lane roundabout ca pacity before calibration. With default parameters, SIDRA and VISSIM tend to underes timate delays and queue lengths for the multi-lane roundabouts under congestion, while RODEL results in higher delay and queue length estimations at most of the entrance approaches.
