In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles...In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.展开更多
The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemen...The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantages on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future. In conclusion, it has a wide application prospect.展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm wi...Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.展开更多
In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes u...In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes unreliable messages along the edges of belief propagation(BP)decoding in the current window to be kept for subsequent window decoding.To improve the reliability of the retained messages during the window transition,a reliable termination method is embedded,where the retained messages undergo more reliable parity checks.Additionally,decoding failure is unavoidable and even causes error propagation when the number of errors exceeds the error-correcting capability of the window.To mitigate this problem,a channel value reuse mechanism is designed,where the received channel values are utilized to reinitialize the window.Furthermore,considering the complexity and performance of decoding,a feasible sliding optimized window decoding(SOWD)scheme is introduced.Finally,simulation results confirm the superior performance of the proposed SOWD scheme in both the waterfall and error floor regions.This work has great potential in the applications of wireless optical communication and fiber optic communication.展开更多
With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutio...With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder.展开更多
Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environ...Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.展开更多
Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in cu...Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.展开更多
Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi...Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems.展开更多
With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored ha...With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored has increased dramatically. The use of compression techniques for these bitstream files is emerging as a key strategy to alleviate the burden on storage resources. Due to the severe resource constraints of space-based electronics and the unique application environment, the simplicity, efficiency and robustness of the decompression circuitry is also a key design consideration. Through comparative analysis current bitstream file compression technologies, this research suggests that the Lempel Ziv Oberhumer (LZO) compression algorithm is more suitable for satellite applications. This paper also delves into the compression process and format of the LZO compression algorithm, as well as the inherent characteristics of configuration bitstream files. We propose an improved algorithm based on LZO for bitstream file compression, which optimises the compression process by refining the format and reducing the offset. Furthermore, a low-cost, robust decompression hardware architecture is proposed based on this method. Experimental results show that the compression speed of the improved LZO algorithm is increased by 3%, the decompression hardware cost is reduced by approximately 60%, and the compression ratio is slightly reduced by 0.47%.展开更多
This paper examines theπ/4QPSK modulation communication transmission system,analyzing the performance advantages and disadvantages ofπ/4QPSK in comparison to QPSK.It also presents a comprehensive FPGA implementation...This paper examines theπ/4QPSK modulation communication transmission system,analyzing the performance advantages and disadvantages ofπ/4QPSK in comparison to QPSK.It also presents a comprehensive FPGA implementation scheme for a modulation communication transmission system,integrating RS channel coding,framing,frequency conversion,and other modules.This design is based on practical research and development requirements.The Xilinx Spartan6 chip board was used for board-level verification.Theπ/4QPSK modulated signal was transmitted via D/A conversion and radio frequency,with the transmitted waveform was looped back for reception.After A/D processing,the correctness of the designed modulation transmission scheme was verified.展开更多
The rapid-cycling synchrotron(RCS)is a crucial device for proton beam acceleration at the China Spallation Neutron Source,operating at a repetition frequency of 25 Hz.The beam power was increased from 100 kW to 140 kW...The rapid-cycling synchrotron(RCS)is a crucial device for proton beam acceleration at the China Spallation Neutron Source,operating at a repetition frequency of 25 Hz.The beam power was increased from 100 kW to 140 kW.This increase makes the on-orbit beam more sensitive to disturbances in various parts of the accelerator,including the RCS magnet power supply system.This paper presents a method for reducing the high-order harmonic current error in resonant power supplies for dipole magnets and examines its impact on the horizontal orbit offset of the beam.It adopts a control scheme that combines high-order harmonic current compensation with PI double-loop control of the resonant power supply.By utilizing the existing digital controller hardware in the RCS power supply system,this study demonstrates how to achieve precise control of the 50 Hz harmonic current output in a cost-effective manner.Ultimately,it enhances performance by reducing the current error by up to 50%and provides methodological support for future upgrades to the power supply system.Such improvements enhance the stability of the RCS,reducing the beam horizontal orbit deviation by at least 19.8%.展开更多
Medical image segmentation has witnessed rapid advancements with the emergence of encoder-decoder based methods.In the encoder-decoder structure,the primary goal of the decoding phase is not only to restore feature ma...Medical image segmentation has witnessed rapid advancements with the emergence of encoder-decoder based methods.In the encoder-decoder structure,the primary goal of the decoding phase is not only to restore feature map resolution,but also to mitigate the loss of feature information incurred during the encoding phase.However,this approach gives rise to a challenge:multiple up-sampling operations in the decoder segment result in the loss of feature information.To address this challenge,we propose a novel network that removes the decoding structure to reduce feature information loss(CBL-Net).In particular,we introduce a Parallel Pooling Module(PPM)to counteract the feature information loss stemming from conventional and pooling operations during the encoding stage.Furthermore,we incorporate a Multiplexed Dilation Convolution(MDC)module to expand the network's receptive field.Also,although we have removed the decoding stage,we still need to recover the feature map resolution.Therefore,we introduced the Global Feature Recovery(GFR)module.It uses attention mechanism for the image feature map resolution recovery,which can effectively reduce the loss of feature information.We conduct extensive experimental evaluations on three publicly available medical image segmentation datasets:DRIVE,CHASEDB and MoNuSeg datasets.Experimental results show that our proposed network outperforms state-of-the-art methods in medical image segmentation.In addition,it achieves higher efficiency than the current network of coding and decoding structures by eliminating the decoding component.展开更多
In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a gene...In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.展开更多
A passive neutron multiplicity measurement device,FH-NCM/S1,based on field-programmable gate arrays(FPGAs),is developed specifically for measuring the mass of plutonium-240(^(240)Pu)in mixed oxide fuel.FH-NCM/S1 adopt...A passive neutron multiplicity measurement device,FH-NCM/S1,based on field-programmable gate arrays(FPGAs),is developed specifically for measuring the mass of plutonium-240(^(240)Pu)in mixed oxide fuel.FH-NCM/S1 adopts an inte-grated approach,combining the shift register analysis mode with the pulse-position timestamp mode using an FPGA.The optimal effective length of the^(3)He neutron detector was determined to be 30 cm,and the thickness of the graphite reflector was ascertained to be 15 cm through MCNP simulations.After fabricating the device,calibration measurements were per-formed using a^(252)Cf neutron source;a detection efficiency of 43.07%and detector die-away time of 55.79μs were observed.Nine samples of plutonium oxide were measured under identical conditions using the FH-NCM/S1 in shift register analysis mode and a plutonium waste multiplicity counter.The obtained double rates underwent corrections for detection efficiency(ε)and double gate fraction(f_(d)),resulting in corrected double rates(D_(c)),which were used to validate the accuracy of the shift register analysis mode.Furthermore,the device exhibited fluctuations in the measurement results,and within a single 20 s measurement,these fluctuations remained below 10%.After 30 cycles,the relative error in the mass of^(240)Pu was less than 5%.Finally,correlation calculations confirmed the robust consistency of both measurement modes.This study holds specific significance for the subsequent design and development of neutron multiplicity devices.展开更多
基金Science and Technology Key Project of Guangzhou(2007Z3-D3101)Production and Research Project of Zhuhai(PC20082002)Technology Innovation Project of Guangdong Province(2008778113)
文摘In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.
文摘The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantages on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future. In conclusion, it has a wide application prospect.
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
文摘Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.
基金supported by the National Natural Science Foundation of China (No.62275193)。
文摘In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes unreliable messages along the edges of belief propagation(BP)decoding in the current window to be kept for subsequent window decoding.To improve the reliability of the retained messages during the window transition,a reliable termination method is embedded,where the retained messages undergo more reliable parity checks.Additionally,decoding failure is unavoidable and even causes error propagation when the number of errors exceeds the error-correcting capability of the window.To mitigate this problem,a channel value reuse mechanism is designed,where the received channel values are utilized to reinitialize the window.Furthermore,considering the complexity and performance of decoding,a feasible sliding optimized window decoding(SOWD)scheme is introduced.Finally,simulation results confirm the superior performance of the proposed SOWD scheme in both the waterfall and error floor regions.This work has great potential in the applications of wireless optical communication and fiber optic communication.
基金Supported by the National Natural Science Foundation of China(No.62103257).
文摘With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder.
基金supported by the National Natural Science Foundation of China under Grant No.62001440。
文摘Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.
基金Project supported by the Natural Science Foundation of Shandong Province,China(Grant No.ZR2021MF049)Joint Fund of Natural Science Foundation of Shandong Province(Grant Nos.ZR2022LLZ012 and ZR2021LLZ001)the Key R&D Program of Shandong Province,China(Grant No.2023CXGC010901)。
文摘Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.
基金supported in part by the National Natural Science Foundation of China under Grant 6226070954Jiangxi Provincial Key R&D Programme under Grant 20244BBG73002.
文摘Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems.
基金supported in part by the National Key Laboratory of Science and Technology on Space Microwave(Grant Nos.HTKJ2022KL504009 and HTKJ2022KL5040010).
文摘With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored has increased dramatically. The use of compression techniques for these bitstream files is emerging as a key strategy to alleviate the burden on storage resources. Due to the severe resource constraints of space-based electronics and the unique application environment, the simplicity, efficiency and robustness of the decompression circuitry is also a key design consideration. Through comparative analysis current bitstream file compression technologies, this research suggests that the Lempel Ziv Oberhumer (LZO) compression algorithm is more suitable for satellite applications. This paper also delves into the compression process and format of the LZO compression algorithm, as well as the inherent characteristics of configuration bitstream files. We propose an improved algorithm based on LZO for bitstream file compression, which optimises the compression process by refining the format and reducing the offset. Furthermore, a low-cost, robust decompression hardware architecture is proposed based on this method. Experimental results show that the compression speed of the improved LZO algorithm is increased by 3%, the decompression hardware cost is reduced by approximately 60%, and the compression ratio is slightly reduced by 0.47%.
文摘This paper examines theπ/4QPSK modulation communication transmission system,analyzing the performance advantages and disadvantages ofπ/4QPSK in comparison to QPSK.It also presents a comprehensive FPGA implementation scheme for a modulation communication transmission system,integrating RS channel coding,framing,frequency conversion,and other modules.This design is based on practical research and development requirements.The Xilinx Spartan6 chip board was used for board-level verification.Theπ/4QPSK modulated signal was transmitted via D/A conversion and radio frequency,with the transmitted waveform was looped back for reception.After A/D processing,the correctness of the designed modulation transmission scheme was verified.
基金supported by the Guangdong Basic and Applied Basic Research Foundation(No.2023B1515120030).
文摘The rapid-cycling synchrotron(RCS)is a crucial device for proton beam acceleration at the China Spallation Neutron Source,operating at a repetition frequency of 25 Hz.The beam power was increased from 100 kW to 140 kW.This increase makes the on-orbit beam more sensitive to disturbances in various parts of the accelerator,including the RCS magnet power supply system.This paper presents a method for reducing the high-order harmonic current error in resonant power supplies for dipole magnets and examines its impact on the horizontal orbit offset of the beam.It adopts a control scheme that combines high-order harmonic current compensation with PI double-loop control of the resonant power supply.By utilizing the existing digital controller hardware in the RCS power supply system,this study demonstrates how to achieve precise control of the 50 Hz harmonic current output in a cost-effective manner.Ultimately,it enhances performance by reducing the current error by up to 50%and provides methodological support for future upgrades to the power supply system.Such improvements enhance the stability of the RCS,reducing the beam horizontal orbit deviation by at least 19.8%.
基金funded by the National Key Research and Development Program of China(Grant 2020YFB1708900)the Fundamental Research Funds for the Central Universities(Grant No.B220201044).
文摘Medical image segmentation has witnessed rapid advancements with the emergence of encoder-decoder based methods.In the encoder-decoder structure,the primary goal of the decoding phase is not only to restore feature map resolution,but also to mitigate the loss of feature information incurred during the encoding phase.However,this approach gives rise to a challenge:multiple up-sampling operations in the decoder segment result in the loss of feature information.To address this challenge,we propose a novel network that removes the decoding structure to reduce feature information loss(CBL-Net).In particular,we introduce a Parallel Pooling Module(PPM)to counteract the feature information loss stemming from conventional and pooling operations during the encoding stage.Furthermore,we incorporate a Multiplexed Dilation Convolution(MDC)module to expand the network's receptive field.Also,although we have removed the decoding stage,we still need to recover the feature map resolution.Therefore,we introduced the Global Feature Recovery(GFR)module.It uses attention mechanism for the image feature map resolution recovery,which can effectively reduce the loss of feature information.We conduct extensive experimental evaluations on three publicly available medical image segmentation datasets:DRIVE,CHASEDB and MoNuSeg datasets.Experimental results show that our proposed network outperforms state-of-the-art methods in medical image segmentation.In addition,it achieves higher efficiency than the current network of coding and decoding structures by eliminating the decoding component.
文摘In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.
基金supported by the National Natural Science Foundation of China(No.42374226)Natural Science Foundation of Jiangxi Province(Nos.20232BAB201043 and 20232BCJ23006)+1 种基金a sub-project of the nuclear energy development project of the China National Defense Science and Industry Bureau‘n-γfusion logging method theory research’(No.20201192-01)the Fundamental Science on Radioactive Geology and Exploration Technology Laboratory(No.2022RGET20)。
文摘A passive neutron multiplicity measurement device,FH-NCM/S1,based on field-programmable gate arrays(FPGAs),is developed specifically for measuring the mass of plutonium-240(^(240)Pu)in mixed oxide fuel.FH-NCM/S1 adopts an inte-grated approach,combining the shift register analysis mode with the pulse-position timestamp mode using an FPGA.The optimal effective length of the^(3)He neutron detector was determined to be 30 cm,and the thickness of the graphite reflector was ascertained to be 15 cm through MCNP simulations.After fabricating the device,calibration measurements were per-formed using a^(252)Cf neutron source;a detection efficiency of 43.07%and detector die-away time of 55.79μs were observed.Nine samples of plutonium oxide were measured under identical conditions using the FH-NCM/S1 in shift register analysis mode and a plutonium waste multiplicity counter.The obtained double rates underwent corrections for detection efficiency(ε)and double gate fraction(f_(d)),resulting in corrected double rates(D_(c)),which were used to validate the accuracy of the shift register analysis mode.Furthermore,the device exhibited fluctuations in the measurement results,and within a single 20 s measurement,these fluctuations remained below 10%.After 30 cycles,the relative error in the mass of^(240)Pu was less than 5%.Finally,correlation calculations confirmed the robust consistency of both measurement modes.This study holds specific significance for the subsequent design and development of neutron multiplicity devices.
