In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles...In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.展开更多
The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemen...The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantages on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future. In conclusion, it has a wide application prospect.展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm wi...Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.展开更多
Traditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters(ADC).However,the cost and power consumption of an entire electronic readout system based on digitizers fo...Traditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters(ADC).However,the cost and power consumption of an entire electronic readout system based on digitizers for a PET scanner are high.To address this problem,a soft-core ADC based on a field-programmable gate array(FPGA)was proposed.An FPGA-based ADC(FPGA-ADC)combines low loss and high performance.To achieve good performance,the FPGA-ADC requires three calibrations:time-to-digital converter(TDC)length calibration,TDC alignment calibration,and TDC-to-ADC calibration.A prototype front-end electronics based on FPGA-ADC was built to evaluate the performance of time-of-flight positron emission tomography(TOF PET)detectors.Each PET detector consists of a LYSO crystal single-ended coupled to a silicon photomultiplier(SiPM).The experimental results show that the full-width at half-maximum(FWHM)energy resolution for 511 keV gamma photons after saturation correction of the SiPM was 12.3%.The FWHM coincidence timing resolution(CTR)of the TOF PET detector with the readout of the front-end electronic prototype is 385.2 ps.FPGA-ADCbased front-end electronics are very promising for multichannel,low-cost,highly integrated,and power-efficient readout electronic systems for radiation detector applications.展开更多
In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes u...In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes unreliable messages along the edges of belief propagation(BP)decoding in the current window to be kept for subsequent window decoding.To improve the reliability of the retained messages during the window transition,a reliable termination method is embedded,where the retained messages undergo more reliable parity checks.Additionally,decoding failure is unavoidable and even causes error propagation when the number of errors exceeds the error-correcting capability of the window.To mitigate this problem,a channel value reuse mechanism is designed,where the received channel values are utilized to reinitialize the window.Furthermore,considering the complexity and performance of decoding,a feasible sliding optimized window decoding(SOWD)scheme is introduced.Finally,simulation results confirm the superior performance of the proposed SOWD scheme in both the waterfall and error floor regions.This work has great potential in the applications of wireless optical communication and fiber optic communication.展开更多
In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a gene...In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.展开更多
With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutio...With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder.展开更多
Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environ...Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.展开更多
Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in cu...Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.展开更多
Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi...Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems.展开更多
A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） mult...A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.展开更多
A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUT...A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.展开更多
基金Science and Technology Key Project of Guangzhou(2007Z3-D3101)Production and Research Project of Zhuhai(PC20082002)Technology Innovation Project of Guangdong Province(2008778113)
文摘In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.
文摘The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantages on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future. In conclusion, it has a wide application prospect.
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
文摘Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.
基金supported by the Key R&D Program of Shandong Province(No.2023SFGC0101)Shandong Excellent Young Scientists Fund Program(Overseas)(No.2023HWYQ-047)+1 种基金the Natural Science Foundation of Shandong Province(No.ZR2022QA039)the National Natural Science Foundation of China(NSFC)(No.U2106202).
文摘Traditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters(ADC).However,the cost and power consumption of an entire electronic readout system based on digitizers for a PET scanner are high.To address this problem,a soft-core ADC based on a field-programmable gate array(FPGA)was proposed.An FPGA-based ADC(FPGA-ADC)combines low loss and high performance.To achieve good performance,the FPGA-ADC requires three calibrations:time-to-digital converter(TDC)length calibration,TDC alignment calibration,and TDC-to-ADC calibration.A prototype front-end electronics based on FPGA-ADC was built to evaluate the performance of time-of-flight positron emission tomography(TOF PET)detectors.Each PET detector consists of a LYSO crystal single-ended coupled to a silicon photomultiplier(SiPM).The experimental results show that the full-width at half-maximum(FWHM)energy resolution for 511 keV gamma photons after saturation correction of the SiPM was 12.3%.The FWHM coincidence timing resolution(CTR)of the TOF PET detector with the readout of the front-end electronic prototype is 385.2 ps.FPGA-ADCbased front-end electronics are very promising for multichannel,low-cost,highly integrated,and power-efficient readout electronic systems for radiation detector applications.
基金supported by the National Natural Science Foundation of China (No.62275193)。
文摘In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes unreliable messages along the edges of belief propagation(BP)decoding in the current window to be kept for subsequent window decoding.To improve the reliability of the retained messages during the window transition,a reliable termination method is embedded,where the retained messages undergo more reliable parity checks.Additionally,decoding failure is unavoidable and even causes error propagation when the number of errors exceeds the error-correcting capability of the window.To mitigate this problem,a channel value reuse mechanism is designed,where the received channel values are utilized to reinitialize the window.Furthermore,considering the complexity and performance of decoding,a feasible sliding optimized window decoding(SOWD)scheme is introduced.Finally,simulation results confirm the superior performance of the proposed SOWD scheme in both the waterfall and error floor regions.This work has great potential in the applications of wireless optical communication and fiber optic communication.
文摘In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.
基金Supported by the National Natural Science Foundation of China(No.62103257).
文摘With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder.
基金supported by the National Natural Science Foundation of China under Grant No.62001440。
文摘Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.
基金Project supported by the Natural Science Foundation of Shandong Province,China(Grant No.ZR2021MF049)Joint Fund of Natural Science Foundation of Shandong Province(Grant Nos.ZR2022LLZ012 and ZR2021LLZ001)the Key R&D Program of Shandong Province,China(Grant No.2023CXGC010901)。
文摘Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.
基金supported in part by the National Natural Science Foundation of China under Grant 6226070954Jiangxi Provincial Key R&D Programme under Grant 20244BBG73002.
文摘Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems.
文摘A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.
文摘A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.
