With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption ...With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.展开更多
Datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. Regularity is a characteris...Datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. Regularity is a characteristic of datapath and the key of the proposed method, where synthesis is tightly combined with placement to make full use of regularity, so that low power consumption is achieved. In This paper, a new concept of Synthesis In Relative Placement (SIRP) is given to deal with the semi-regularity in some datapath. Experimental results of a sample circuit validated the proposed method.展开更多
Since the dawn of the Internet of Things(IoT),data and system security has been the major concern for developers.Because most IoT devices operate on 8-bit controllers with limited storage and computation power,encrypt...Since the dawn of the Internet of Things(IoT),data and system security has been the major concern for developers.Because most IoT devices operate on 8-bit controllers with limited storage and computation power,encryption and decryption need to be implemented at the transmitting and receiving ends,respectively,using lightweight ciphers.We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture.The ANU cipher is implemented at 4-,8-,16-,and 32-bit datapath sizes on four different field-programmable gate array(FPGA)platforms under the same implementation condition,and the results are compared on every performance metric.Unlike previous ANU architectures,the new architectures have parallel substitution boxes(S-boxes)for high throughput and hardware optimization.With these different datapath designs,ANU cipher proves to be the obvious choice for implementing security in extremely resourceconstrained systems.展开更多
文摘With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.
基金Project (No. 2002 AA1Z1140) supported by the Hi-Tech Research and Development Program (863) of China and the Fork Ying Tong Education Foundation (No. 94031), China
文摘Datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. Regularity is a characteristic of datapath and the key of the proposed method, where synthesis is tightly combined with placement to make full use of regularity, so that low power consumption is achieved. In This paper, a new concept of Synthesis In Relative Placement (SIRP) is given to deal with the semi-regularity in some datapath. Experimental results of a sample circuit validated the proposed method.
文摘Since the dawn of the Internet of Things(IoT),data and system security has been the major concern for developers.Because most IoT devices operate on 8-bit controllers with limited storage and computation power,encryption and decryption need to be implemented at the transmitting and receiving ends,respectively,using lightweight ciphers.We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture.The ANU cipher is implemented at 4-,8-,16-,and 32-bit datapath sizes on four different field-programmable gate array(FPGA)platforms under the same implementation condition,and the results are compared on every performance metric.Unlike previous ANU architectures,the new architectures have parallel substitution boxes(S-boxes)for high throughput and hardware optimization.With these different datapath designs,ANU cipher proves to be the obvious choice for implementing security in extremely resourceconstrained systems.
