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An adaptive pipelining scheme for H.264/AVC CABAC decoder 被引量:1
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作者 陈杰 Ding Dandan Yu Lu 《High Technology Letters》 EI CAS 2013年第4期391-397,共7页
An adaptive pipelining scheme for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoder for high definition(HD) applications is proposed to solve data hazard problems coming from the data dependenci... An adaptive pipelining scheme for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoder for high definition(HD) applications is proposed to solve data hazard problems coming from the data dependencies in CABAC decoding process.An efficiency model of CABAC decoding pipeline is derived according to the analysis of a common pipeline.Based on that,several adaptive strategies are provided.The pipelining scheme with these strategies can be adaptive to different types of syntax elements(SEs) and the pipeline will not stall during decoding process when these strategies are adopted.In addition,the decoder proposed can fully support H.264/AVC high4:2:2 profile and the experimental results show that the efficiency of decoder is much higher than other architectures with one engine.Taking both performance and cost into consideration,our design makes a good tradeoff compared with other work and it is sufficient for HD real-time decoding. 展开更多
关键词 H.264/AVC context-based adaptive binary arithmetic coding (CABAC) adaptive PIPELINE data dependency data hazard
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High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoding 被引量:1
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作者 Kai HUANG De MA +2 位作者 Rong-jie YAN Hai-tong GE Xiao-lang YAN 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2013年第6期449-463,共15页
Context-based adaptive binary arithmetic coding(CABAC) is the major entropy-coding algorithm employed in H.264/AVC.In this paper,we present a new VLSI architecture design for an H.264/AVC CABAC decoder,which optimizes... Context-based adaptive binary arithmetic coding(CABAC) is the major entropy-coding algorithm employed in H.264/AVC.In this paper,we present a new VLSI architecture design for an H.264/AVC CABAC decoder,which optimizes both decode decision and decode bypass engines for high throughput,and improves context model allocation for efficient external memory access.Based on the fact that the most possible symbol(MPS) branch is much simpler than the least possible symbol(LPS) branch,a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost.A look-ahead context index(ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch.A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding features.In addition,to lower the frequency of memory access,we reorganize the context models in external memory and use three circular buffers to cache the context models,neighboring information,and bit stream,respectively.A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory latency.Experimental results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology,and that it achieves an average data decoding rate of 1.5 bins/cycle. 展开更多
关键词 H.264/AVC context-based adaptive binary arithmetic coding(CABAC) Decoder VLSI
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CABAC算术编码器硬件优化实现 被引量:1
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作者 王瑞 姜宏旭 李波 《北京航空航天大学学报》 EI CAS CSCD 北大核心 2009年第6期678-682,共5页
为了解决上下文自适应二进制算术编码器(CABAC,Context-based Adaptive Binary Arithmetic Coder)硬件实现吞吐率难以提高的问题,提出了基于数据流动态特性的电路优化方法.通过建立算法的数据流模型,提取出限制硬件实现性能的数据流反... 为了解决上下文自适应二进制算术编码器(CABAC,Context-based Adaptive Binary Arithmetic Coder)硬件实现吞吐率难以提高的问题,提出了基于数据流动态特性的电路优化方法.通过建立算法的数据流模型,提取出限制硬件实现性能的数据流反馈环路.针对上下文环路,采用3条迭代周期不同的子环路更新具有不同依赖周期的上下文变量,提高了时钟频率和吞吐率;对于字节打包环路,通过提取一类可简化电路结构的数据元素,并为之构建快速旁路,增加了环路的处理速度.基于上述方法并辅以基本的电路优化手段,设计实现在现场可编程门阵列(FPGA,Field-Programmable Gate Array)平台上频率可达309MHz,并且每个时钟周期处理一个编码符号. 展开更多
关键词 算术编码 上下文自适应二进制算术编码器 硬件结构 现场可编程门阵列
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