Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FET...Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.展开更多
Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field ...Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.展开更多
基金supported in part by the Hong Kong Research Impact Fund(Grant No.R6008-18)the Shen-zhen Science and Technology Innovation Commission(Grant No.SGDX2020110309460101).
文摘Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.
文摘Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.
