The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,o...The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,only one compiler may not be sufficient to encrypt data in an acceptable time.In this paper,we consider the problem of several compilers and the objective is tofind an algorithm that can give an efficient schedule for the givenfiles to be compiled by the compilers.The main objective of the work is to minimize the gap in the total size of assignedfiles between compilers.This minimization ensures the fair distribution offiles to different compilers.This problem is considered to be a very hard problem.This paper presents two research axes.Thefirst axis is related to architecture.We propose a novel pre-compiler architecture in this context.The second axis is algorithmic development.We develop six algorithms to solve the problem,in this context.These algorithms are based on the dispatching rules method,decomposition method,and an iterative approach.These algorithms give approximate solutions for the studied problem.An experimental result is imple-mented to show the performance of algorithms.Several indicators are used to measure the performance of the proposed algorithms.In addition,five classes are proposed to test the algorithms with a total of 2350 instances.A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm.The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic(ISL)with a percentage equal to 97.7%and an average running time equal to 0.148 s.All other algorithms did not exceed 22%as a percentage.The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic(ILS)with a percentage equal to 21,4%and an average running time equal to 0.150 s.展开更多
Translation validation was invented in the 90＇s by Pnueli et al. as a technique to formally verify the correctness of code generators. Rather than certifying the code generator or exhaustively qualifying it, translat...Translation validation was invented in the 90＇s by Pnueli et al. as a technique to formally verify the correctness of code generators. Rather than certifying the code generator or exhaustively qualifying it, translation validators attempt to verify that program transformations preserve semantics. In this work, we adopt this approach to formally verify that the clock semantics and data dependence are preserved during the compilation of the Signal compiler. Translation valida- tion is implemented for every compilation phase from the initial phase until the latest phase where the executable code is generated, by proving the transformation in each phase of the compiler preserves the semantics. We represent the clock semantics, the data dependence of a program and its trans- formed counterpart as first-order formulas which are called clock models and synchronous dependence graphs （SDGs）, respectively. We then introduce clock refinement and depen- dence refinement relations which express the preservations of clock semantics and dependence, as a relation on clock mod- els and SDGs, respectively. Our validator does not require any instrumentation or modification of the compiler, nor any rewriting of the source program.展开更多
Should the article be accepted and published by Agricultural Science&Technology,the author hereby grants exclusively to the editorial department of Agricultural Science&Technology the digital reproduction,dist...Should the article be accepted and published by Agricultural Science&Technology,the author hereby grants exclusively to the editorial department of Agricultural Science&Technology the digital reproduction,distribution,compilation and information network transmission rights.展开更多
New Era New Xizang The series of books has been compiled by educators from nine colleges affiliated with Xizang Minzu University over 18 months.The work is organized into six volumes.It systematically summarizes the r...New Era New Xizang The series of books has been compiled by educators from nine colleges affiliated with Xizang Minzu University over 18 months.The work is organized into six volumes.It systematically summarizes the remarkable achievements of Xizang in various domains,including economic development.展开更多
In compliance with“Copyright Law of the People’s Republic of China”,it is agreed by the author(s)of the said article as follows upon signing of this statement:The said article shall be published in Journal of Trans...In compliance with“Copyright Law of the People’s Republic of China”,it is agreed by the author(s)of the said article as follows upon signing of this statement:The said article shall be published in Journal of Trans-lational Neuroscience.The author(s)shall grant the fol-lowing worldwide exclusive rights carried by the said article in different languages to Journal of Translational Neuroscience free of charge:reproductions,distribution,electronic dissemination,translation and compilation.The author(s)authorize(s)Journal of Translational Neu-roscience to register the said article(including all the in-termedia)with the proper copyright authorities.展开更多
Should the article be accepted and published by Agricultural Science&Technology,the author hereby grants exclusively to the editorial department of Agricultural Science&Technology the digital reproduction,dist...Should the article be accepted and published by Agricultural Science&Technology,the author hereby grants exclusively to the editorial department of Agricultural Science&Technology the digital reproduction,distribution,compilation and information network transmission rights.展开更多
Traditional quantum circuit scheduling approaches underutilize the inherent parallelism of quantum computation in the Noisy Intermediate-Scale Quantum(NISQ)era,overlook the inter-layer operations can be further parall...Traditional quantum circuit scheduling approaches underutilize the inherent parallelism of quantum computation in the Noisy Intermediate-Scale Quantum(NISQ)era,overlook the inter-layer operations can be further parallelized.Based on this,two quantum circuit scheduling optimization approaches are designed and integrated into the quantum circuit compilation process.Firstly,we introduce the Layered Topology Scheduling Approach(LTSA),which employs a greedy algorithm and leverages the principles of topological sorting in graph theory.LTSA allocates quantum gates to a layered structure,maximizing the concurrent execution of quantum gate operations.Secondly,the Layerwise Conflict Resolution Approach(LCRA)is proposed.LCRA focuses on utilizing directly executable quantum gates within layers.Through the insertion of SWAP gates and conflict resolution checks,it minimizes conflicts and enhances parallelism,thereby optimizing the overall computational efficiency.Experimental findings indicate that LTSA and LCRA individually achieve a noteworthy reduction of 51.1%and 53.2%,respectively,in the number of inserted SWAP gates.Additionally,they contribute to a decrease in hardware gate overhead by 14.7%and 15%,respectively.Considering the intricate nature of quantum circuits and the temporal dependencies among different layers,the amalgamation of both approaches leads to a remarkable 51.6%reduction in inserted SWAP gates and a 14.8%decrease in hardware gate overhead.These results underscore the efficacy of the combined LTSA and LCRA in optimizing quantum circuit compilation.展开更多
VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduce...VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is front-end tool of the VHDL high level synthesis and mixed level simulation system developed by the Research Center of ASIC of BIT.展开更多
Prototype landscape refers to the impressive scenes that one has experienced in his/her living environment before 20 years old.Based on the analysis of the existing literature,the authors compiled a standard scale typ...Prototype landscape refers to the impressive scenes that one has experienced in his/her living environment before 20 years old.Based on the analysis of the existing literature,the authors compiled a standard scale type questionnaire by means of a field survey,which was about the influences of prototype landscape on one's landscape perception.Taking Likert scale as the main part,this questionnaire analyzed the influence of prototype landscape on landscape perception from perception,attitude,and behavior dimensions.In order to further improve its rationality,the authors tested some other aspects of this questionnaire,including logic validity,construct validity,congeniality reliability,split-half reliability,etc..The results validated that the questionnaire possessed good theoretical structure and validity target,which can evaluate various aspects of prototype landscape on one's landscape perception in an effective and reliable way.Therefore,the questionnaire put forward by this study not only enriched the studies of prototype landscape on landscape designing,but also provided an effective tool for quantitative analysis of "the influences of prototype landscape on one's landscape perception".展开更多
This paper briefly introduces the systemic structure of Vocational English series--Basic English, and puts forwards the four key compiling principles, namely, system, cognition, practicality and interest.
In view of lake scenic areas with abundant tourist resources but less-developed economy,contradictions between the urgency of its tourist resource development and complexity of urban-rural planning compilation were an...In view of lake scenic areas with abundant tourist resources but less-developed economy,contradictions between the urgency of its tourist resource development and complexity of urban-rural planning compilation were analyzed,and also limitations summarized as insufficient time and fund.Statutory planning contents included in the integrated compilation system were elaborated,and compilation of the integrated planning for the Longhe Lake Scenic Area in the Taihang Mountains was taken for example to introduce planning concepts of the compilation technical system.Considering characteristics of the study area,"regionality" was stressed as the foundation of planning compilation,concise,convenient and practical planning compilation contents were advocated and further explained from the perspectives of compiling by layer and category.In view of this,it is necessary to apply integrated compilation mode under certain circumstances,so as to provide a new approach for the planning compilation of other regions in China and enhance economic and social development of local areas.展开更多
基金The author would like to thank the Deanship of Scientific Research at Majmaah University for supporting this work under Project Number No.R-2022-85.
文摘The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,only one compiler may not be sufficient to encrypt data in an acceptable time.In this paper,we consider the problem of several compilers and the objective is tofind an algorithm that can give an efficient schedule for the givenfiles to be compiled by the compilers.The main objective of the work is to minimize the gap in the total size of assignedfiles between compilers.This minimization ensures the fair distribution offiles to different compilers.This problem is considered to be a very hard problem.This paper presents two research axes.Thefirst axis is related to architecture.We propose a novel pre-compiler architecture in this context.The second axis is algorithmic development.We develop six algorithms to solve the problem,in this context.These algorithms are based on the dispatching rules method,decomposition method,and an iterative approach.These algorithms give approximate solutions for the studied problem.An experimental result is imple-mented to show the performance of algorithms.Several indicators are used to measure the performance of the proposed algorithms.In addition,five classes are proposed to test the algorithms with a total of 2350 instances.A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm.The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic(ISL)with a percentage equal to 97.7%and an average running time equal to 0.148 s.All other algorithms did not exceed 22%as a percentage.The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic(ILS)with a percentage equal to 21,4%and an average running time equal to 0.150 s.
文摘Translation validation was invented in the 90＇s by Pnueli et al. as a technique to formally verify the correctness of code generators. Rather than certifying the code generator or exhaustively qualifying it, translation validators attempt to verify that program transformations preserve semantics. In this work, we adopt this approach to formally verify that the clock semantics and data dependence are preserved during the compilation of the Signal compiler. Translation valida- tion is implemented for every compilation phase from the initial phase until the latest phase where the executable code is generated, by proving the transformation in each phase of the compiler preserves the semantics. We represent the clock semantics, the data dependence of a program and its trans- formed counterpart as first-order formulas which are called clock models and synchronous dependence graphs （SDGs）, respectively. We then introduce clock refinement and depen- dence refinement relations which express the preservations of clock semantics and dependence, as a relation on clock mod- els and SDGs, respectively. Our validator does not require any instrumentation or modification of the compiler, nor any rewriting of the source program.
文摘Should the article be accepted and published by Agricultural Science&Technology,the author hereby grants exclusively to the editorial department of Agricultural Science&Technology the digital reproduction,distribution,compilation and information network transmission rights.
文摘New Era New Xizang The series of books has been compiled by educators from nine colleges affiliated with Xizang Minzu University over 18 months.The work is organized into six volumes.It systematically summarizes the remarkable achievements of Xizang in various domains,including economic development.
文摘In compliance with“Copyright Law of the People’s Republic of China”,it is agreed by the author(s)of the said article as follows upon signing of this statement:The said article shall be published in Journal of Trans-lational Neuroscience.The author(s)shall grant the fol-lowing worldwide exclusive rights carried by the said article in different languages to Journal of Translational Neuroscience free of charge:reproductions,distribution,electronic dissemination,translation and compilation.The author(s)authorize(s)Journal of Translational Neu-roscience to register the said article(including all the in-termedia)with the proper copyright authorities.
文摘Should the article be accepted and published by Agricultural Science&Technology,the author hereby grants exclusively to the editorial department of Agricultural Science&Technology the digital reproduction,distribution,compilation and information network transmission rights.
基金funded by the Natural Science Foundation of Heilongjiang Province(Grant No.LH2022F035)the Cultivation Programme for Young Innovative Talents in Ordinary Higher Education Institutions of Heilongjiang Province(Grant No.UNPYSCT-2020212)the Cultivation Programme for Young Innovative Talents in Scientific Research of Harbin University of Commerce(Grant No.2023-KYYWF-0983).
文摘Traditional quantum circuit scheduling approaches underutilize the inherent parallelism of quantum computation in the Noisy Intermediate-Scale Quantum(NISQ)era,overlook the inter-layer operations can be further parallelized.Based on this,two quantum circuit scheduling optimization approaches are designed and integrated into the quantum circuit compilation process.Firstly,we introduce the Layered Topology Scheduling Approach(LTSA),which employs a greedy algorithm and leverages the principles of topological sorting in graph theory.LTSA allocates quantum gates to a layered structure,maximizing the concurrent execution of quantum gate operations.Secondly,the Layerwise Conflict Resolution Approach(LCRA)is proposed.LCRA focuses on utilizing directly executable quantum gates within layers.Through the insertion of SWAP gates and conflict resolution checks,it minimizes conflicts and enhances parallelism,thereby optimizing the overall computational efficiency.Experimental findings indicate that LTSA and LCRA individually achieve a noteworthy reduction of 51.1%and 53.2%,respectively,in the number of inserted SWAP gates.Additionally,they contribute to a decrease in hardware gate overhead by 14.7%and 15%,respectively.Considering the intricate nature of quantum circuits and the temporal dependencies among different layers,the amalgamation of both approaches leads to a remarkable 51.6%reduction in inserted SWAP gates and a 14.8%decrease in hardware gate overhead.These results underscore the efficacy of the combined LTSA and LCRA in optimizing quantum circuit compilation.
文摘VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is front-end tool of the VHDL high level synthesis and mixed level simulation system developed by the Research Center of ASIC of BIT.
文摘Prototype landscape refers to the impressive scenes that one has experienced in his/her living environment before 20 years old.Based on the analysis of the existing literature,the authors compiled a standard scale type questionnaire by means of a field survey,which was about the influences of prototype landscape on one's landscape perception.Taking Likert scale as the main part,this questionnaire analyzed the influence of prototype landscape on landscape perception from perception,attitude,and behavior dimensions.In order to further improve its rationality,the authors tested some other aspects of this questionnaire,including logic validity,construct validity,congeniality reliability,split-half reliability,etc..The results validated that the questionnaire possessed good theoretical structure and validity target,which can evaluate various aspects of prototype landscape on one's landscape perception in an effective and reliable way.Therefore,the questionnaire put forward by this study not only enriched the studies of prototype landscape on landscape designing,but also provided an effective tool for quantitative analysis of "the influences of prototype landscape on one's landscape perception".
文摘This paper briefly introduces the systemic structure of Vocational English series--Basic English, and puts forwards the four key compiling principles, namely, system, cognition, practicality and interest.
文摘In view of lake scenic areas with abundant tourist resources but less-developed economy,contradictions between the urgency of its tourist resource development and complexity of urban-rural planning compilation were analyzed,and also limitations summarized as insufficient time and fund.Statutory planning contents included in the integrated compilation system were elaborated,and compilation of the integrated planning for the Longhe Lake Scenic Area in the Taihang Mountains was taken for example to introduce planning concepts of the compilation technical system.Considering characteristics of the study area,"regionality" was stressed as the foundation of planning compilation,concise,convenient and practical planning compilation contents were advocated and further explained from the perspectives of compiling by layer and category.In view of this,it is necessary to apply integrated compilation mode under certain circumstances,so as to provide a new approach for the planning compilation of other regions in China and enhance economic and social development of local areas.
