A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and it...A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.展开更多
The digital processing signal is one of the subdivisions of the analog digital converter interface;data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion r...The digital processing signal is one of the subdivisions of the analog digital converter interface;data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.展开更多
池黄高铁联调联试阶段发现小区切换异常现象,针对该现象采用多方位筛查方法,对比分析不同终端模块、基站设备,结合实验室环境下仿真实验进行研究。实验结果揭示,某车载终端在处理基站识别码(Base Station Identity Code,BSIC)时存在显...池黄高铁联调联试阶段发现小区切换异常现象,针对该现象采用多方位筛查方法,对比分析不同终端模块、基站设备,结合实验室环境下仿真实验进行研究。实验结果揭示,某车载终端在处理基站识别码(Base Station Identity Code,BSIC)时存在显著的解析异常,尤其是以0结尾的BSIC码容易引发误码,导致切换失败,对比多条线路,均表现出一定概率的解析异常。因此提出规避以0结尾的BSIC码作为解决方案,可在设计阶段避免使用,或在联调期间暂时规避,而运营车辆不使用该模块也不受影响。此解决方案强调了参数选择和设备兼容性对系统稳定性的关键作用,为高速铁路无线通信系统设计和运维提供指导。展开更多
文摘A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.
文摘The digital processing signal is one of the subdivisions of the analog digital converter interface;data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.
文摘池黄高铁联调联试阶段发现小区切换异常现象,针对该现象采用多方位筛查方法,对比分析不同终端模块、基站设备,结合实验室环境下仿真实验进行研究。实验结果揭示,某车载终端在处理基站识别码(Base Station Identity Code,BSIC)时存在显著的解析异常,尤其是以0结尾的BSIC码容易引发误码,导致切换失败,对比多条线路,均表现出一定概率的解析异常。因此提出规避以0结尾的BSIC码作为解决方案,可在设计阶段避免使用,或在联调期间暂时规避,而运营车辆不使用该模块也不受影响。此解决方案强调了参数选择和设备兼容性对系统稳定性的关键作用,为高速铁路无线通信系统设计和运维提供指导。
