QR and LU decompositions are the most important matrix decomposition algorithms. Many studies work on accelerating these algorithms by FPGA or ASIC in a case by case style. In this paper, we propose a unified framewor...QR and LU decompositions are the most important matrix decomposition algorithms. Many studies work on accelerating these algorithms by FPGA or ASIC in a case by case style. In this paper, we propose a unified framework for the matrix decomposition algorithms, combining three QR decomposition algorithms and LU algorithm with pivoting into a unified linear array structure. The QR and LU decomposition algorithms exhibit the same two-level loop structure and the same data dependency. Utilizing the similarities in loop structure and data dependency of matrix decomposition, we unify a fine-grained algorithm for all four matrix decomposition algorithms. Furthermore, we present a unified co-processor structure with a scalable linear array of processing elements （PEs）, in which four types of PEs are same in the structure of memory channels and PE connections, but the only difference exists in the internal structure of data path. Our unified co-processor, which is IEEE 32-bit floating-point precision, is implemented and mapped onto a Xilinx Virtex5 FPGA chip. Experimental results show that our co-processors can achieve speedup of 2.3 to 14.9 factors compared to a Pentium Dual CPU with double SSE threads.展开更多
面对物联网的快速发展,需要低延时、高性能的处理器来实现关键数据的传输和保护,同时要提高处理器的硬件安全,减少非法用户对处理器的攻击。结合当前开源第五代精简指令集(Reduced Instruction Set Computing-Five,RISC-V)处理器架构优...面对物联网的快速发展,需要低延时、高性能的处理器来实现关键数据的传输和保护,同时要提高处理器的硬件安全,减少非法用户对处理器的攻击。结合当前开源第五代精简指令集(Reduced Instruction Set Computing-Five,RISC-V)处理器架构优点,与现场可编程门阵列(Field Programmable Gate Array,FPGA)相结合,设计了异构处理器,提出了基于密码的安全启动模型。首先,细化RISC-V异构处理器的体系结构,设计轻量级密码启动安全模型TrustZone,实现处理器性能与安全的平衡,并结合FPGA的优点,实现定制化的专用协议与业务通信。其次,提出当前RISC-V异构处理器可实现的便捷途径,并基于此进行模型搭建和测试验证。验证结果表明,虽然采用TrustZone安全度量后处理器启动时间有所增加,但针对轻量级的处理器应用场景,在增强处理器安全的前提下,该启动时间开销是可以接受的。展开更多
基于Cell处理器的异构多核架构及软件显式管理的多级存储层次,使其面临编程困难和性能难以有效发挥等问题.现有基于Cell/B.E.的编程模型多侧重于支持类似于流处理的"批量访存"(bulk data transfer)应用,传统非规则访存应用性...基于Cell处理器的异构多核架构及软件显式管理的多级存储层次,使其面临编程困难和性能难以有效发挥等问题.现有基于Cell/B.E.的编程模型多侧重于支持类似于流处理的"批量访存"(bulk data transfer)应用,传统非规则访存应用性能较低.通过扩展Cell/B.E.访存库增强协处理单元的自主作用,以协处理单元为中心建立Cell计算平台上的MPI和弱一致性Pthread分层并行编程运行时支持.分层的运行时支持结构及扩展后的Cell/B.E.访存库使模型具有更好的效率和可扩展性,并且提高了非规则应用的性能;模型中的MPI方便了大量传统并行应用向新架构的移植及开发,而弱一致性Pthread则为MPI提供高效的任务运行时管理支持及为系统级用户提供对架构全面控制的编程接口.实验结果表明,提出的运行时支持技术不仅可适应不同应用的要求,同时借助访存库中的剖分优化机制可有效地挖掘Cell/B.E.架构性能.展开更多
在服务器端加入GPU或MIC等协处理器可以提升性能。但是,传统Web服务器端软件不能充分发挥多核CPU+MIC协处理器异构硬件体系的性能。为解决该问题,针对该硬件体系提出了一种新的Web服务器软件框架。该软件框架基于分阶段事件驱动模型,将...在服务器端加入GPU或MIC等协处理器可以提升性能。但是,传统Web服务器端软件不能充分发挥多核CPU+MIC协处理器异构硬件体系的性能。为解决该问题,针对该硬件体系提出了一种新的Web服务器软件框架。该软件框架基于分阶段事件驱动模型,将部分动态请求调度至MIC协处理器执行,并可在多核CPU和MIC协处理器上并行处理动态请求。同时,通过采用自适应调度算法兼顾了CPU和MIC协处理器间的负载均衡。仿真实验表明,该模型在平均响应时间、吞吐量等方面均优于传统的基于先到先服务(First Come First Served,FCFS)的Web服务器软件模型。展开更多
基金Supported by the National Natural Science Foundation of China under Grant Nos.60633050 and 60833004,60903057the National High-Technology Research and Development 863 Program of China under Grant No.2009AA01Z101
文摘QR and LU decompositions are the most important matrix decomposition algorithms. Many studies work on accelerating these algorithms by FPGA or ASIC in a case by case style. In this paper, we propose a unified framework for the matrix decomposition algorithms, combining three QR decomposition algorithms and LU algorithm with pivoting into a unified linear array structure. The QR and LU decomposition algorithms exhibit the same two-level loop structure and the same data dependency. Utilizing the similarities in loop structure and data dependency of matrix decomposition, we unify a fine-grained algorithm for all four matrix decomposition algorithms. Furthermore, we present a unified co-processor structure with a scalable linear array of processing elements （PEs）, in which four types of PEs are same in the structure of memory channels and PE connections, but the only difference exists in the internal structure of data path. Our unified co-processor, which is IEEE 32-bit floating-point precision, is implemented and mapped onto a Xilinx Virtex5 FPGA chip. Experimental results show that our co-processors can achieve speedup of 2.3 to 14.9 factors compared to a Pentium Dual CPU with double SSE threads.
文摘基于Cell处理器的异构多核架构及软件显式管理的多级存储层次,使其面临编程困难和性能难以有效发挥等问题.现有基于Cell/B.E.的编程模型多侧重于支持类似于流处理的"批量访存"(bulk data transfer)应用,传统非规则访存应用性能较低.通过扩展Cell/B.E.访存库增强协处理单元的自主作用,以协处理单元为中心建立Cell计算平台上的MPI和弱一致性Pthread分层并行编程运行时支持.分层的运行时支持结构及扩展后的Cell/B.E.访存库使模型具有更好的效率和可扩展性,并且提高了非规则应用的性能;模型中的MPI方便了大量传统并行应用向新架构的移植及开发,而弱一致性Pthread则为MPI提供高效的任务运行时管理支持及为系统级用户提供对架构全面控制的编程接口.实验结果表明,提出的运行时支持技术不仅可适应不同应用的要求,同时借助访存库中的剖分优化机制可有效地挖掘Cell/B.E.架构性能.
文摘在服务器端加入GPU或MIC等协处理器可以提升性能。但是,传统Web服务器端软件不能充分发挥多核CPU+MIC协处理器异构硬件体系的性能。为解决该问题,针对该硬件体系提出了一种新的Web服务器软件框架。该软件框架基于分阶段事件驱动模型,将部分动态请求调度至MIC协处理器执行,并可在多核CPU和MIC协处理器上并行处理动态请求。同时,通过采用自适应调度算法兼顾了CPU和MIC协处理器间的负载均衡。仿真实验表明,该模型在平均响应时间、吞吐量等方面均优于传统的基于先到先服务(First Come First Served,FCFS)的Web服务器软件模型。
