It is necessary to perform the test of system on chip,the test scheduling determines the test start and finishing time of every core in the system on chip such that the overall test time is minimized.A new test schedu...It is necessary to perform the test of system on chip,the test scheduling determines the test start and finishing time of every core in the system on chip such that the overall test time is minimized.A new test scheduling approach based on chaotic ant colony algorithm is presented in this paper.The optimization model of test scheduling was studied,the model uses the information such as the scale of test sets of both cores and user defined logic.An approach based on chaotic ant colony algorithm was proposed to solve the optimization model of test scheduling.The test of signal integrity faults such as crosstalk were also investigated when performing the test scheduling.Experimental results on many circuits show that the proposed approach can be used to solve test scheduling problems.展开更多
In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity o...In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.展开更多
In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of micr...In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.展开更多
In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant...In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..展开更多
As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead a...As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.展开更多
Paper-based flexible surface-enhanced Raman scattering(SERS) chips have been demonstrated to have great potential for future practical applications in point-of-care testing(POCT) due to the potentials of massive fabri...Paper-based flexible surface-enhanced Raman scattering(SERS) chips have been demonstrated to have great potential for future practical applications in point-of-care testing(POCT) due to the potentials of massive fabrication, low cost, efficient sample collection and short signal acquisition time. In this work,common filter paper and Ag@Si O2 core-shell nanoparticles(NP) have been utilized to fabricate SERS chips based on shell-isolated nanoparticle-enhanced Raman spectroscopy(SHINERS). The SERS performance of the chips for POCT applications was systematically investigated. We used crystal violet as the model molecule to study the influence of the size of the Ag core and the thickness of the Si O2 coating layer on the SERS activity and then the morphology optimized Ag@Si O2 core-shell NPs was employed to detect thiram. By utilizing the smartphone as a miniaturized Raman spectral analyzer, high SERS sensitivity of thiram with a detection limit of 10^-9 M was obtained. The study on the stability of the SERS chips shows that a Si O2 shell of 3 nm can effectively protect the as-prepared SERS chips against oxidation in ambient atmosphere without seriously weakening the SERS sensitivity. Our results indicated that the SERS chips by SHINERS had great potential of practical application, such as pesticide residues detection in POCT.展开更多
The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are un...The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.展开更多
A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updat...A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.展开更多
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test an...A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.展开更多
We have presented a three dimensional optical protein chip that fulfills the demanding for point-of-care diagnostics in terms of ease-of-use (one step assay), miniaturization (5 μl). The artful combination of magneti...We have presented a three dimensional optical protein chip that fulfills the demanding for point-of-care diagnostics in terms of ease-of-use (one step assay), miniaturization (5 μl). The artful combination of magnetic nanoparticles on chip and total internal reflection imaging (TIRI) technology permits the sensitive and rapid detection of hs-CRP (high-sensitivity C-reactive protein). The whole test was complete within 10 min using “all in one step” assay with a limit of detection of 0.1 ng/mL hs-CRP. The measuring range for hs-CRP could be extended to 10 ng/mL. The chip can also be used to detect more parameters in blood samples.展开更多
基金supported by Guangdong Provincial Natural Science Foundation of China (7005833)
文摘It is necessary to perform the test of system on chip,the test scheduling determines the test start and finishing time of every core in the system on chip such that the overall test time is minimized.A new test scheduling approach based on chaotic ant colony algorithm is presented in this paper.The optimization model of test scheduling was studied,the model uses the information such as the scale of test sets of both cores and user defined logic.An approach based on chaotic ant colony algorithm was proposed to solve the optimization model of test scheduling.The test of signal integrity faults such as crosstalk were also investigated when performing the test scheduling.Experimental results on many circuits show that the proposed approach can be used to solve test scheduling problems.
基金supported by the National High Technology Research and Development Program of China (863 Program) (2002AA1Z1490)Specialized Research Fund for the Doctoral Program of Higher Education (20040486049)the University Cooperative Research Fund of Huawei Technology Co., Ltd
文摘In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.
文摘In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.
文摘In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..
基金Project supported by the Applied Materials Foundation Project of Science and Technology Commission of Shanghai Mu-nicipality (Grant No.08700741000)the System Design on Chip Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)+1 种基金the Leading Academic Discipline Project of Shanghai Municipal Education Committee(Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.
基金supported financially by the National Natural Science Foundation of China (No. 51802060)the Shenzhen Innovation Project (No. KQJSCX20170726104623185)the Shenzhen Peacock Group (KQTD20170809110344233)
文摘Paper-based flexible surface-enhanced Raman scattering(SERS) chips have been demonstrated to have great potential for future practical applications in point-of-care testing(POCT) due to the potentials of massive fabrication, low cost, efficient sample collection and short signal acquisition time. In this work,common filter paper and Ag@Si O2 core-shell nanoparticles(NP) have been utilized to fabricate SERS chips based on shell-isolated nanoparticle-enhanced Raman spectroscopy(SHINERS). The SERS performance of the chips for POCT applications was systematically investigated. We used crystal violet as the model molecule to study the influence of the size of the Ag core and the thickness of the Si O2 coating layer on the SERS activity and then the morphology optimized Ag@Si O2 core-shell NPs was employed to detect thiram. By utilizing the smartphone as a miniaturized Raman spectral analyzer, high SERS sensitivity of thiram with a detection limit of 10^-9 M was obtained. The study on the stability of the SERS chips shows that a Si O2 shell of 3 nm can effectively protect the as-prepared SERS chips against oxidation in ambient atmosphere without seriously weakening the SERS sensitivity. Our results indicated that the SERS chips by SHINERS had great potential of practical application, such as pesticide residues detection in POCT.
基金Supported by the National Natural Science Fund of China (No.60876028)the key Project of Natural Science Foundation of the Anhui Higher Education Institutions (No.KJ2010A280)
文摘The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.
文摘A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.
基金Project supported by the SDC Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)the AM Foundation Project of Science and Technology Commission of Shanghai Municipality (Grant No.08700741000)+1 种基金the Leading Academic Discipline Project of Shanghai Education Commission (Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
文摘We have presented a three dimensional optical protein chip that fulfills the demanding for point-of-care diagnostics in terms of ease-of-use (one step assay), miniaturization (5 μl). The artful combination of magnetic nanoparticles on chip and total internal reflection imaging (TIRI) technology permits the sensitive and rapid detection of hs-CRP (high-sensitivity C-reactive protein). The whole test was complete within 10 min using “all in one step” assay with a limit of detection of 0.1 ng/mL hs-CRP. The measuring range for hs-CRP could be extended to 10 ng/mL. The chip can also be used to detect more parameters in blood samples.
