All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for ...All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-to-digital (A/D) conversion system through generating low noise, linear chirp distribution and flat super-continuum (SC). Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.展开更多
An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integra...An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.展开更多
In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock...In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.展开更多
An optical fiber control and transmission module is designed and realized based on Virtex-7 field programmable gata array(FPGA), which can be applied in multi-channel broadband digital receivers. The module consists o...An optical fiber control and transmission module is designed and realized based on Virtex-7 field programmable gata array(FPGA), which can be applied in multi-channel broadband digital receivers. The module consists of sampling data transfer submodule and multi-channel synchronous sampling control submodule. The sampling data transmission in 4× fiber link channel is realized with the self-defined transfer protocol. The measured maximum data rate is 4.97 Gbyte/s. By connecting coherent clocks to the transmitter and receiver endpoints and using the self-defined transfer protocol, multi-channel sampling control signals transferred in optical fibers can be received synchronously by each analog-to-digital converter(ADC) with high accuracy and strong anti-interference ability. The module designed in this paper has certain reference value in increasing the transmission bandwidth and the synchronous sampling accuracy of multi-channel broadband digital receivers.展开更多
Sampling rate conversion finds great use in the area of multirate signal processing, communications system, speech processing system, etc. In this paper, we describe a structure of 72 MHz/54 MHz sampling rate conversi...Sampling rate conversion finds great use in the area of multirate signal processing, communications system, speech processing system, etc. In this paper, we describe a structure of 72 MHz/54 MHz sampling rate conversion system which is applied to HDTV system. First, we discuss the theoretical model of a 4/3 conversion scheme and then design the hardware structure implemented in parallel and illustrate the subsystem structure in detail. Finally, the phase diagrams are presented to show the relations between the clocks.展开更多
The state of the p-n junction is very important to explain the performances of a solar cell. Some works give the influence of the electric field on the junction capacitance. However, these works do not relate the qual...The state of the p-n junction is very important to explain the performances of a solar cell. Some works give the influence of the electric field on the junction capacitance. However, these works do not relate the quality of the p-n junction under the electic field. The present manuscript is about a theoretical modelling of the p-n junction capacitance behavior of the polycrystalline silicon solar cell under an integration of the external electrical field source. An external electrical source is integrated in a solar cell system. The electronic carriers charge generated in the solar cell crossed mainly the junction with the great strength external electrical field. In open circuit, this crossing of the electronic charge carriers causes the thermal heating of the p-n junction by Joule effect. The p-n junction capacitance plotted versus the junction dynamic velocity and the photo-voltage for different external electrical fields. The electric field causes the decrease of the photo-voltage mainly the open-circuit photo-voltage. The decrease of the photo-voltage translates the narrowing of the Space Charge Region (SCR). The average value of the external electric field used in this study is not sufficient to cause the breakdown of the p-n junction of the solar cell system under integration of the external electrical field production source. The increase of the electrical field causes rather the narrowing of the SCR. That can provide an improvement of the solar cell’s electrical outputs.展开更多
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ...A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.展开更多
A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods...A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm.展开更多
This paper presents a flexible and high speed digital scan converter (DSC) with the ability to handle high frequency ultrasound imaging in real-time. The characteristics in imaging system such as focus length of trans...This paper presents a flexible and high speed digital scan converter (DSC) with the ability to handle high frequency ultrasound imaging in real-time. The characteristics in imaging system such as focus length of transducer, the swing radius and sampling length etc. could be changed easily in compliance with the researcher's application based on this flexible digital scan converter. Linear interpolation is employed to achieve the coordinate transformations algorithm. Custom-built software is programmed to preliminarily handle the algorithm according to different ultrasound imaging applications. High performance FPGA will implement high speed interpolation calculation based on the preliminary data which are stored in the DDR2 SDRAM from the software. 64 bit 66 MHz PCI is employed to accomplish high speed data transmission. Experiment has shown that more than 500 frame rate could be achieved based on this high speed digital scan converter. The designed flexible and high speed digital scan converter could be used in current FPGA based high frequency ultrasound imaging system.展开更多
A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also pro...A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.展开更多
In this research paper,we have presented variable area type capacitive sensor signal conditioning system for angular displacement measurement and for this purpose we have used timer LM555 based astable multivibrator a...In this research paper,we have presented variable area type capacitive sensor signal conditioning system for angular displacement measurement and for this purpose we have used timer LM555 based astable multivibrator and universal frequency to digital converter (UFDC). Due to variation in angular displacement in the variable area type capacitor which is connected in the timer based astable circuit,capacitance changes which in turn changes the time period of the timer circuit output. The time period of the timer output waveform is linear with the capacitance and hence linear with angular displacement. The timer output is further processed with UFDC for the measurement. The experimental results show that the time period is linear with the angular displacement in the range of 0- 180° and the uncertainty we should associate it with this average time period value is the standard deviation of the mean,often called the standard error (SE),which is ± 0.023 μs. Because of the simplicity,this measurement system can be used in both electronic and industrial instrumentation.展开更多
This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slop...Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.展开更多
It is proved that the bearing history display is an effective method to detect weak signal. There is an interface between multibeam data and brightness modulation display system in digital sonar. The system gain obtai...It is proved that the bearing history display is an effective method to detect weak signal. There is an interface between multibeam data and brightness modulation display system in digital sonar. The system gain obtained from signal processing system may be lost in this interface. A right choice of conversion algorithm will reduce this lose to minimum. The Grey Scale Conversion ( GSC) algorithm proposed in this paper is a real time digital operation technique. This technique can be used to improve the detection ability for weak signals, in the meantime there is no serious effect on strong signal detection. The method described in this papr is easy to implement in hardware. The simulation results with a computer show a good agreement with the theoretical analysis. A brief outline of hardware design is also illustrated.展开更多
基金supported by the Doctoral Program of Higher Education Research Fund (No.1101.01.001.672)
文摘All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-to-digital (A/D) conversion system through generating low noise, linear chirp distribution and flat super-continuum (SC). Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.
基金supported by the Fundamental Research Funds for the Central Universities,China(Grant No.FRF-TP-15-030A1)China Postdoctoral Science Foundation(Grant No.2015M580978)
文摘An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.
基金The National Natural Science Foundation ofChina(No.60402003)The National High Technology Research and Development Pro-gram of China(863Program)(No.2002AA745120)
文摘In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.
文摘An optical fiber control and transmission module is designed and realized based on Virtex-7 field programmable gata array(FPGA), which can be applied in multi-channel broadband digital receivers. The module consists of sampling data transfer submodule and multi-channel synchronous sampling control submodule. The sampling data transmission in 4× fiber link channel is realized with the self-defined transfer protocol. The measured maximum data rate is 4.97 Gbyte/s. By connecting coherent clocks to the transmitter and receiver endpoints and using the self-defined transfer protocol, multi-channel sampling control signals transferred in optical fibers can be received synchronously by each analog-to-digital converter(ADC) with high accuracy and strong anti-interference ability. The module designed in this paper has certain reference value in increasing the transmission bandwidth and the synchronous sampling accuracy of multi-channel broadband digital receivers.
文摘Sampling rate conversion finds great use in the area of multirate signal processing, communications system, speech processing system, etc. In this paper, we describe a structure of 72 MHz/54 MHz sampling rate conversion system which is applied to HDTV system. First, we discuss the theoretical model of a 4/3 conversion scheme and then design the hardware structure implemented in parallel and illustrate the subsystem structure in detail. Finally, the phase diagrams are presented to show the relations between the clocks.
文摘The state of the p-n junction is very important to explain the performances of a solar cell. Some works give the influence of the electric field on the junction capacitance. However, these works do not relate the quality of the p-n junction under the electic field. The present manuscript is about a theoretical modelling of the p-n junction capacitance behavior of the polycrystalline silicon solar cell under an integration of the external electrical field source. An external electrical source is integrated in a solar cell system. The electronic carriers charge generated in the solar cell crossed mainly the junction with the great strength external electrical field. In open circuit, this crossing of the electronic charge carriers causes the thermal heating of the p-n junction by Joule effect. The p-n junction capacitance plotted versus the junction dynamic velocity and the photo-voltage for different external electrical fields. The electric field causes the decrease of the photo-voltage mainly the open-circuit photo-voltage. The decrease of the photo-voltage translates the narrowing of the Space Charge Region (SCR). The average value of the external electric field used in this study is not sufficient to cause the breakdown of the p-n junction of the solar cell system under integration of the external electrical field production source. The increase of the electrical field causes rather the narrowing of the SCR. That can provide an improvement of the solar cell’s electrical outputs.
文摘A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
基金Supported by the Knowledge Innovation Program of the Chinese Academy of Sciences(No.KJCX2-YW-N27)National Natural Science Foundation of China(Nos.11205153 and 11175176)
文摘A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm.
文摘This paper presents a flexible and high speed digital scan converter (DSC) with the ability to handle high frequency ultrasound imaging in real-time. The characteristics in imaging system such as focus length of transducer, the swing radius and sampling length etc. could be changed easily in compliance with the researcher's application based on this flexible digital scan converter. Linear interpolation is employed to achieve the coordinate transformations algorithm. Custom-built software is programmed to preliminarily handle the algorithm according to different ultrasound imaging applications. High performance FPGA will implement high speed interpolation calculation based on the preliminary data which are stored in the DDR2 SDRAM from the software. 64 bit 66 MHz PCI is employed to accomplish high speed data transmission. Experiment has shown that more than 500 frame rate could be achieved based on this high speed digital scan converter. The designed flexible and high speed digital scan converter could be used in current FPGA based high frequency ultrasound imaging system.
文摘A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.
文摘In this research paper,we have presented variable area type capacitive sensor signal conditioning system for angular displacement measurement and for this purpose we have used timer LM555 based astable multivibrator and universal frequency to digital converter (UFDC). Due to variation in angular displacement in the variable area type capacitor which is connected in the timer based astable circuit,capacitance changes which in turn changes the time period of the timer circuit output. The time period of the timer output waveform is linear with the capacitance and hence linear with angular displacement. The timer output is further processed with UFDC for the measurement. The experimental results show that the time period is linear with the angular displacement in the range of 0- 180° and the uncertainty we should associate it with this average time period value is the standard deviation of the mean,often called the standard error (SE),which is ± 0.023 μs. Because of the simplicity,this measurement system can be used in both electronic and industrial instrumentation.
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
文摘Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.
文摘It is proved that the bearing history display is an effective method to detect weak signal. There is an interface between multibeam data and brightness modulation display system in digital sonar. The system gain obtained from signal processing system may be lost in this interface. A right choice of conversion algorithm will reduce this lose to minimum. The Grey Scale Conversion ( GSC) algorithm proposed in this paper is a real time digital operation technique. This technique can be used to improve the detection ability for weak signals, in the meantime there is no serious effect on strong signal detection. The method described in this papr is easy to implement in hardware. The simulation results with a computer show a good agreement with the theoretical analysis. A brief outline of hardware design is also illustrated.
