An effective discrete artificial bee colony(DABC) algorithm is proposed for the flow shop scheduling problem with intermediate buffers(IBFSP) in order to minimize the maximum completion time(i.e makespan). The effecti...An effective discrete artificial bee colony(DABC) algorithm is proposed for the flow shop scheduling problem with intermediate buffers(IBFSP) in order to minimize the maximum completion time(i.e makespan). The effective combination of the insertion and swap operator is applied to producing neighborhood individual at the employed bee phase. The tournament selection is adopted to avoid falling into local optima, while, the optimized insert operator embeds in onlooker bee phase for further searching the neighborhood solution to enhance the local search ability of algorithm. The tournament selection with size 2 is again applied and a better selected solution will be performed destruction and construction of iterated greedy(IG) algorithm, and then the result replaces the worse one. Simulation results show that our algorithm has a better performance compared with the HDDE and CHS which were proposed recently. It provides the better known solutions for the makespan criterion to flow shop scheduling problem with limited buffers for the Car benchmark by Carlier and Rec benchmark by Reeves. The convergence curves show that the algorithm not only has faster convergence speed but also has better convergence value.展开更多
Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue （IQ）, which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accoun...Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue （IQ）, which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands （called 2OP instructions） are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer （WIB） and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT proeessor,the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.展开更多
基金Projects(61174040,61104178,61374136) supported by the National Natural Science Foundation of ChinaProject(12JC1403400) supported by Shanghai Commission of Science and Technology,ChinaProject supported by the Fundamental Research Funds for the Central Universities,China
文摘An effective discrete artificial bee colony(DABC) algorithm is proposed for the flow shop scheduling problem with intermediate buffers(IBFSP) in order to minimize the maximum completion time(i.e makespan). The effective combination of the insertion and swap operator is applied to producing neighborhood individual at the employed bee phase. The tournament selection is adopted to avoid falling into local optima, while, the optimized insert operator embeds in onlooker bee phase for further searching the neighborhood solution to enhance the local search ability of algorithm. The tournament selection with size 2 is again applied and a better selected solution will be performed destruction and construction of iterated greedy(IG) algorithm, and then the result replaces the worse one. Simulation results show that our algorithm has a better performance compared with the HDDE and CHS which were proposed recently. It provides the better known solutions for the makespan criterion to flow shop scheduling problem with limited buffers for the Car benchmark by Carlier and Rec benchmark by Reeves. The convergence curves show that the algorithm not only has faster convergence speed but also has better convergence value.
文摘Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue （IQ）, which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands （called 2OP instructions） are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer （WIB） and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT proeessor,the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.
